Changing PLL settings

[segher]

I'm trying to change PLL settings on the XC-2 board, since it boots as 125MHz core
frequency, and that's not quite what I want (the official firmware uses 400MHz as
well, btw).

That all goes great (a write to system switch reg 6) -- but then it resets. Is this
documented? It's not totally unexpected of course, it will take a while for the PLL
to become stable again (unless you do very special tricks).

But, now my problem: most often I'm running from JTAG, so a reset will throw
me straight into a WAITEU in the on-chip ROM again. My JTAG tools do not know
whether the program they run will reset, and I'd rather not have to teach them;
it would be a lot neater if there was some trick I could use so it wouldn't enter
the ROM code again (or I could programmatically get it out).

Any ideas?

[ale500]

That the chip resets is documented (page 4 in the XS1-G Clock Frequency Control pdf) But how to remain connected via JTAG after the reset... I do not know. Can you program the new frequency using an XN file ?

[segher]

That the chip resets is documented (page 4 in the XS1-G Clock Frequency Control pdf)

Ah, it's not in the datasheet or xsystem.pdf; I'll hunt down that file, thanks.

But how to remain connected via JTAG after the reset... I do not know.

It's not about staying connected. The problem is that the cores (or the whole chip?)
reset, and the cores then run the bootup sequence again; using the old pin strapping
for boot mode, it seems. The ROM code then runs the "boot from JTAG" code, which
is basically just WAITEU; so it hangs until I kick it. I don't want to kick it (mostly because
this exact same (binary) code runs on many other boards, which don't need this).

Hrm, maybe I can sneakily write the strap pins reg to boot from RAM instead :-)

Can you program the new frequency using an XN file ?

I don't use the desktoptools; I use JTAG directly. I also don't use C or XC or anything
like that :-)


Segher

[segher]

So that didn't work out; writing to PS 030b gives an exception #6.

My next try would be to have a timer go off after writing the PLL, but all
resources are cleared on the reset. Rats. I guess I have a challenge :-)