Difficulties with XN file on a dual XEF232 board

[azs]

Hi there !

I'm working on a custom PCBoard where we put two XEF232 devices. The aim is to link them to act as an 8-Tiles device.
On the hardware side, only first XMOS is attached to a QSPI flash. The second one is aimed to boot as a slave to the first. JTAG is linked TDO -> TDI, with TCK/TMS in //.
Each XMOS have a 24MHz clock driving it (the same clock, from two distinct pin of an FPGA)

I have routed on the PCB two XLINKs (2-wires) between devices, just in case. First XLINK is between Tile#1 pins, link[1]. The other between Tile#2 pins, link[5].

I'm not an expert in XN files, but after reading some docs and some other topics and examples, I think (well, really, I "think" ;) ) I got the idea.
However, I can't get through a compilation without errors..... so I need your help :)


If I declare both links :

Code: Select all

  <Links>
    <Link Encoding="2wire" Delays="5clk" Flags="XSCOPE">
      <LinkEndpoint NodeId="0" Link="XL0"/>
      <LinkEndpoint NodeId="8" Chanend="1"/>
    </Link>
    <Link Encoding="2wire" Delays="3clk">
      <LinkEndpoint NodeId="1" Link="1"/>
      <LinkEndpoint NodeId="5" Link="1"/>
    </Link>
    <Link Encoding="2wire" Delays="3clk">
      <LinkEndpoint NodeId="2" Link="5"/>
      <LinkEndpoint NodeId="6" Link="5"/>
    </Link>
  </Links>

I got the following error :
..\.\AVB-Module.xn: Error: XN11049 Network positioning failed (unsupported topology).
xmake[1]: *** [bin/Release/AVB-Module.xe] Error 1
xmake: *** [bin/Release/AVB-Module.xe] Error 2



If I declare a single link :

Code: Select all

  <Links>
    <Link Encoding="2wire" Delays="5clk" Flags="XSCOPE">
      <LinkEndpoint NodeId="0" Link="XL0"/>
      <LinkEndpoint NodeId="8" Chanend="1"/>
    </Link>
    <Link Encoding="2wire" Delays="3clk">
      <LinkEndpoint NodeId="1" Link="1"/>
      <LinkEndpoint NodeId="5" Link="1"/>
    </Link>
  </Links>

I got the following error :
Assertion failed: !up, file ..\XNLoader\XNLoader.cpp, line 4449
xmake[1]: *** [bin/Release/AVB-Module.xe] Error 1
xmake: *** [bin/Release/AVB-Module.xe] Error 2


Well okay and now the funny thing, as I was making some test for writing this post, I managed to compile with the "other" link (alone) déclaration :

Code: Select all

  <Links>
    <Link Encoding="2wire" Delays="5clk" Flags="XSCOPE">
      <LinkEndpoint NodeId="0" Link="XL0"/>
      <LinkEndpoint NodeId="8" Chanend="1"/>
    </Link>
    <Link Encoding="2wire" Delays="3clk">
      <LinkEndpoint NodeId="2" Link="5"/>
      <LinkEndpoint NodeId="6" Link="5"/>
    </Link>
  </Links>

Please find the .XN file for reference.
Anybody can explain this behaviour ?

Thanks for your help.

AVB-Module.xn

[Joe]

This is a pretty complicated system but I'll try my best to help.

<Link Encoding="2wire" Delays="3clk">
<LinkEndpoint NodeId="1" Link="1"/>
<LinkEndpoint NodeId="5" Link="1"/>
</Link>

This link is probably the issue the tools are complaining about at least, it's connecting two notional "USB tiles" together which isn't valid (node Ids 1 and 5).

We have to be careful to be precise about node ids versus tile ids. Links are tied to nodes not tiles in general.

It's not clear specifically which link pins you have connected between devices. My guess is you have X0L1 of the first package connected to X2L5 on the second package? Do you have this wired as a full 5 wire link (5 in each direction so 10 total)?

[Joe]

Oh I see you said the links a 2 wire. That is a bit of an issue for booting - the chip can only boot from XL0 in 2 wire mode.

The system might still be able to run as an 8 tile system if you are loading via JTAG however.

[azs]

Thanks Joe for such valuable information !

Yes this is 2 wire links only.
First link is on X1D52 to X1D55 on both devices (don't work)
Second link is on X2D52 to X2D55 on both devices (work okay)

I was not aware of such limitations (USB tiles, booting limitations.....). Is there any official documentation that explains all this ? I did not found many things and to be honest, make this design with many "suppositions", but maybe I've missed an official doc ?

I can confirm, at this stage, that downloading via JTAG a simple program that blinks LEDs (one on each XMOS) works well, it is seen as an 8-Tiles device, and both LEDs blinks correctly.

I then tried to programme the QSPI flash, ended quickly with this error message :
spanning-xn-v0-35fe50ad: Error: XN11188 Network is not fully connected (no route from node "0" to node "4")

From what I understand from your post, I will never be able to boot from flash with this hardware platform ? Should I attach a rope to the ceiling right now, or is there tips and tricks I can try ?

"the chip can only boot from XL0 in 2 wire mode" : can you explain this in more details ? What is XL0 ?
This points me to something in the .xn file.

I think theses links description are pretty clear for me, as I can find a correspondance in the pinout mapping :

Code: Select all

        <Link Encoding="5wire" Delays="3clk">
          <LinkEndpoint NodeId="0" Link="7"/>
          <LinkEndpoint NodeId="2" Link="0"/>
        </Link>
        <Link Encoding="5wire" Delays="3clk">
          <LinkEndpoint NodeId="0" Link="4"/>
          <LinkEndpoint NodeId="2" Link="3"/>
        </Link>
        <Link Encoding="5wire" Delays="3clk">
          <LinkEndpoint NodeId="0" Link="6"/>
          <LinkEndpoint NodeId="2" Link="1"/>
        </Link>
        <Link Encoding="5wire" Delays="3clk">
          <LinkEndpoint NodeId="0" Link="5"/>
          <LinkEndpoint NodeId="2" Link="2"/>
        </Link>

But I cannot correctly figure-out theses :

Code: Select all

        <Link Encoding="5wire">
          <LinkEndpoint NodeId="0" Link="8" Delays="52clk,52clk"/>
          <LinkEndpoint NodeId="1" Link="XL0" Delays="1clk,1clk"/>
        </Link>
        <Link Encoding="5wire">
          <LinkEndpoint NodeId="2" Link="8" Delays="52clk,52clk"/>
          <LinkEndpoint NodeId="3" Link="XL0" Delays="1clk,1clk"/>
        </Link>

What is link "8" and "XL0" ? Why 52clk ?

Thanks a lot for your help !

[azs]

See in the datasheet of XEF232, schematic checklist, subsection H.9 Multi device design :
Devices that boot from link have, for example, X0D06 pulled high and have link XL0 connected to a device to boot from (Section 8).

Damned should have re-read this document before !
Does XL0 refers to Xlink0, i.e. pins X0D40 to X0D43 ?

Maybe a chance for me, on my second (slave) XMOS (i.e. the one that should boot from the master), theses 4 pins are available on test-points on my board.
But it's still limited to a 2-wire mode link and not a 5-wire....

On which Xlink of Master XMOS can I try to connect these pins ? I have the same 4-pins available on the Master (well, available not strictly as it goes on the XTAG debug connector, but I can disconnect wires from the probe connector if it can save my prototype board )
Should I made a try ? Or is 5-wires mandatory ?

Thanks,

[Joe]

Yes XL0 = Xlink0, yes X0D40-43.

Good that they are on test points. If you look at a datasheet for the 232 without flash here:

https://www.xmos.com/download/XE232-102 ... (1_16).pdf

See figure 9, you can see all the boot mode options. You can see in there if you want to boot from link you pull X0D06 high and it will try to boot from XL0 in 2 wire mode.

You should be able to connect this to any spare 2w link on the other device. But a most "normal" config would be to connect to a link overlapping tile2 or tile3 IO if you have one spare.

<Link Encoding="5wire">
<LinkEndpoint NodeId="0" Link="8" Delays="52clk,52clk"/>
<LinkEndpoint NodeId="1" Link="XL0" Delays="1clk,1clk"/>
</Link>
<Link Encoding="5wire">
<LinkEndpoint NodeId="2" Link="8" Delays="52clk,52clk"/>
<LinkEndpoint NodeId="3" Link="XL0" Delays="1clk,1clk"/>
</Link>

These are links connecting the main node (with 2 tiles on it) to the notional USB node. Link8 is a internal on die only link. 52 clk, 52 clk sets the inter and intra token delay of the link to 52 core/tile clocks (i.e. quite a slow link). This link is mostly for register traffic IIRC so doesn't need to be fast. The USB node runs on a much slower clock so I think that's why the link needs to be run so slow.

[azs]

Thanks Joe ! You're the best
I will immediately try to route my spare XL0 and see if I can reach my goal.

I will give you a feedback, positive or not, but one more time thanks for your valuable help.