Yes, A low frequency external clock is used to drive the internal phase locked loop (PLL) of XS1-L devices and obtain the system clock. A number of system clock dividers are then used on the system clock to derive the clocks for the xCORE tiles, the switch and the reference clock. The PLL’s initial settings are determined by the state of mode pins on the XS1-L device. Refer to XS1-L Clock frequency control document for additional information.
Does a change of the system frequency in the XN file change Topic is solved
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- XCore Expert
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- XCore Expert
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