Our second video based around the XMP-64 shows how Jamie Hanlon, a student undertaking a research project at University has developed programs to help him write test software to explore chip to chip communication.
Key points covered include chip latency, barrier synchronisations, and an example program to show how easy it is to program in a parallel nature utilising as many processors/cores as you need using XMOS processors and the XC programming language.
The XMP-64 consists of 16 quad core G-series XMOS chips (64 processors in total) arranged in a hypercube allowing for very fast communication of data between processors (1.6 billion bits per second can flow between hypercube edges).
The XMP-64 can therefore execute 25 billion instructions per second. To find out more, please watch the video or visit xmos.com.
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