I have never used strobed ports, so I will look into that.
Are you familiar with the sync() statement? I noticed you never used it in your code chunks, but the SPI code I started with had it, so I kept it. I do get junk if I comment that out. According to the xs1.h file, the sync statement will block untill all pending outputs are completed.After you execute:
sclk <: 0xAA;
sclk <: 0xAA;
sclk <: 0xAA;
sclk <: 0xAA;
sync(sclk);
spi_ss <: 1;
You cannot expect spi_ss <: 1 to execute after all the proceeding 4 statements instead it will probably come after 2nd downfalling clock.
I output 4x 8 bit values. The sync statement would wait for the edges to be clocked out. At least that is how I understand it. Only when sclk is done outputting the buffer will sync() stop blocking, and then spi_ss is pulsed (after it is completed), and the same thing happens.
With the sync() method, the fifo should be clear after the first 4 bytes (all outputted). It then repeats, reaching 32 clock cycles for the miso port (8 bytes, 2x doing the above).Also since the fifo is 4 deep the processor should block after 4x writes to sclk. I'm not sure how it's possible to trigger pmiso :> data with a 32bit clock expectation with only 16 clock cycles.
If it wasn't reaching 32 cycles, it would just hang forever (took me awhile to get it to not do that).
If I can confirm it is working properly now (on actual hardware), shouldn't I be guaranteed it will always work? The same code is just looped a bunch.
Thank you all for your input!