Hello,
I want to run the Ethernet Slice the old Diamound port on the U16 Board. The following pin assignment has been made in the ethernet_board_conf.h.
#if defined(ETHERNET_USE_ALT_DIAMOUND)
#define ETHERNET_DEFAULT_TILE tile[1]
#define PORT_ETH_RXCLK on tile[1]: XS1_PORT_1J
#define PORT_ETH_RXD on tile[1]: XS1_PORT_32A
#define PORT_ETH_TXD on tile[1]: XS1_PORT_4E
#define PORT_ETH_RXDV on tile[1]: XS1_PORT_1K
#define PORT_ETH_TXEN on tile[1]: XS1_PORT_1L
#define PORT_ETH_TXCLK on tile[1]: XS1_PORT_1I
#define PORT_ETH_MDIO on tile[1]: XS1_PORT_1M
#define PORT_ETH_MDC on tile[1]: XS1_PORT_1N
#define PORT_ETH_INT on tile[1]: XS1_PORT_1O
#define PORT_ETH_ERR on tile[1]: XS1_PORT_1P
Data is sent but the you receive your on port 32A does not work.
Although 32A0,32A1,32A2,32A3 (B6, B7, A6, A7) are together. The port is not used by others.
At the Port Square the Ethernet board works with the following assignment.
// Default to SQUARE
#define SMI_COMBINE_MDC_MDIO 1
#define SMI_MDC_BIT 0
#define SMI_MDIO_BIT 1
#define ETHERNET_DEFAULT_TILE tile[1]
#define PORT_ETH_RXCLK on tile[1]: XS1_PORT_1B
#define PORT_ETH_RXD on tile[1]: XS1_PORT_4A
#define PORT_ETH_TXD on tile[1]: XS1_PORT_4B
#define PORT_ETH_RXDV on tile[1]: XS1_PORT_1C
#define PORT_ETH_TXEN on tile[1]: XS1_PORT_1F
#define PORT_ETH_TXCLK on tile[1]: XS1_PORT_1G
#define PORT_ETH_MDIOC on tile[1]: XS1_PORT_4C
#define PORT_ETH_MDIOFAKE on tile[1]: XS1_PORT_8A
#define PORT_ETH_ERR on tile[1]: XS1_PORT_4D
Anyone have experience here where the problem is?
thank you so much
Marco
Ethernet Slice on alt DIAMOND Port to U-16 Board
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Code: Select all
#define PORT_ETH_RXD on tile[1]: XS1_PORT_32A
See 2.12.5 of USB U16 Slicekit manual
P32A0 is available. B6 pin on PCIe.
P32A1 is available. B7 pin on PCIe.
P32A2..P32A6 are missing and not available.
P32A7 is available. A6 pin on PCIe.
P32A8 is available. A7 pin on PCIe.
The above may explain your observations. The porting of the Ethernet slice on this ALT DIAMOND slot will be a bit more of a challenge due to the break up of the ports. Perhaps you can use as you have defined and consider to stitch the port data back to required format to replicate the original IP. Likely the data writes are also not being sent to the Ethernet PHY correctly for the same reason. Have to review the Ethernet slice schematic and then compare to the PCIe pins applied to interface with the PHY. Will comment more after this review.
Also, do note the reference to J14 to allow for the use of the ALT DIAMOND slot:
2.11 Diamond/Alt Diamond Slot
The I/Os connected to the Diamond slot can be changed to an alternative configuration
known as Alt Diamond, this is controlled by setting the jumper J14.
The Diamond configuration exposes 16 bits of the 32-bit port, which can be useful
for applications requiring a wide bus, the Alt Diamond configuration exposes more
1-bit ports.
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The PHY requires a 4 bit wide port. The jumper j14 is set.
In Manual an error is included. On page 11, the pin assignment is described correctly. A32 forms with B6, B7, A6, A7, a 4 bit wide port. The problem to be being accessed here on a 32-bit wide port.
See Manual page 21 A6 and A7 are here individually assigned wrong for the config Old Diamond.According to the manual 32A7 and 32A8 connected. This is wrong, they are actually connected to 32A2 and A32A3.
I have tried this with the GPIO Slice. The ports B6, B7, A6, A7 are connected to the LEDs 0-3. In the Old Diamond config let this be controlled with 4bit.
greetings Marco
In Manual an error is included. On page 11, the pin assignment is described correctly. A32 forms with B6, B7, A6, A7, a 4 bit wide port. The problem to be being accessed here on a 32-bit wide port.
See Manual page 21 A6 and A7 are here individually assigned wrong for the config Old Diamond.According to the manual 32A7 and 32A8 connected. This is wrong, they are actually connected to 32A2 and A32A3.
I have tried this with the GPIO Slice. The ports B6, B7, A6, A7 are connected to the LEDs 0-3. In the Old Diamond config let this be controlled with 4bit.
greetings Marco
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I believe from memory that the Ethernet code may uses it's 4bit RX/TX ports in 32 bit buffered mode which would never work with a 32 bit port, unless you rewrite the low level RX/TX driving stack.
regards
Al
regards
Al
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yes !
in buffered port:32 p_mii_rxd; /**< MII RX data wire */
precisely, it is a 32-bit shift register defines what does not work with a 32bit port.
It can not be larger than 32bit.
regards Marco
in buffered port:32 p_mii_rxd; /**< MII RX data wire */
precisely, it is a 32-bit shift register defines what does not work with a 32bit port.
It can not be larger than 32bit.
regards Marco
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On XMOS devices, if the port width 4 bits and is applied with a buffered 32 bit access then it will take 8 clock cycles to consume the FIFO depth of 32 bits.
For example, if the 32 bit FIFO value to be written is 0x12345678 to a 4 bit physical port then
on clock cycle
t : 8 will be written to the 4 bit physical port
t+1 : 7 will be written to the 4 bit physical port
t+2 : 6 will be written to the 4 bit physical port
t+3 : 5 will be written to the 4 bit physical port
t+4 : 4 will be written to the 4 bit physical port
t+5 : 3 will be written to the 4 bit physical port
t+6 : 2 will be written to the 4 bit physical port
t+7 : 1 will be written to the 4 bit physical port
all done automatically via hardware while you can continue to do other work which is a very nice to have feature.
Now if you have a 32 bit port definition with a 32 bit buffered access then
on clock cycle
t : all 32 bits will be written to the 32 bit physical port so a single clock cycle will write the full 32 bit value
but since this Ethernet hardware is designed with a 4 bit access to the Ethernet PHY, 28 bits will be lost in this single clock cycle write. Only the lower 4 bits will be actually written to the PHY.
The Ethernet hardware (TX) is 4 bits and that appears to be fine on the ALT DIAMOND slot since 4 bits are also applied on the hardware. So the TX logic should be fine in this IP.
The issue is with the RX mapping since the ALT DIAMOND slot is now a 32 bit physical port. The IP will fall apart as posted due to the 32 bit port width.
From a quick review, the Ethernet IP and related documentation is written in a format that only twins can understand. Having invested months in trying to understand the XMOS SDRAM IP which we now have partially working on the StartKit (to be released to the public once complete and/or documented with details of the issues related to the StartKit support) - this project is probably similar with complications. However, does not hurt to try your ideas to support the ALT DIAMOND slot with this IP. For sure you will learn more about the XMOS devices in the process. Being a snow day locally - will try the same IP and write back if anything positive to offer.
In the meantime, please review the following:
https://www.xmos.com//download/public/a ... 0.a%29.pdf
https://www.xmos.com//download/public/a ... 0.a%29.pdf
https://www.xmos.com/download/public/XM ... 28E%29.pdf
* Review section 6 of this documentation
Please also review the attached documentation to note the observed errors / typos present in the USB U16 Slice Kit manual of which you have raised one of the errors:
For example, if the 32 bit FIFO value to be written is 0x12345678 to a 4 bit physical port then
on clock cycle
t : 8 will be written to the 4 bit physical port
t+1 : 7 will be written to the 4 bit physical port
t+2 : 6 will be written to the 4 bit physical port
t+3 : 5 will be written to the 4 bit physical port
t+4 : 4 will be written to the 4 bit physical port
t+5 : 3 will be written to the 4 bit physical port
t+6 : 2 will be written to the 4 bit physical port
t+7 : 1 will be written to the 4 bit physical port
all done automatically via hardware while you can continue to do other work which is a very nice to have feature.
Now if you have a 32 bit port definition with a 32 bit buffered access then
on clock cycle
t : all 32 bits will be written to the 32 bit physical port so a single clock cycle will write the full 32 bit value
but since this Ethernet hardware is designed with a 4 bit access to the Ethernet PHY, 28 bits will be lost in this single clock cycle write. Only the lower 4 bits will be actually written to the PHY.
The Ethernet hardware (TX) is 4 bits and that appears to be fine on the ALT DIAMOND slot since 4 bits are also applied on the hardware. So the TX logic should be fine in this IP.
The issue is with the RX mapping since the ALT DIAMOND slot is now a 32 bit physical port. The IP will fall apart as posted due to the 32 bit port width.
From a quick review, the Ethernet IP and related documentation is written in a format that only twins can understand. Having invested months in trying to understand the XMOS SDRAM IP which we now have partially working on the StartKit (to be released to the public once complete and/or documented with details of the issues related to the StartKit support) - this project is probably similar with complications. However, does not hurt to try your ideas to support the ALT DIAMOND slot with this IP. For sure you will learn more about the XMOS devices in the process. Being a snow day locally - will try the same IP and write back if anything positive to offer.
In the meantime, please review the following:
https://www.xmos.com//download/public/a ... 0.a%29.pdf
https://www.xmos.com//download/public/a ... 0.a%29.pdf
https://www.xmos.com/download/public/XM ... 28E%29.pdf
* Review section 6 of this documentation
Please also review the attached documentation to note the observed errors / typos present in the USB U16 Slice Kit manual of which you have raised one of the errors:
You do not have the required permissions to view the files attached to this post.
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The SliceKit selector sheet Seems to indicate it will work in Alt Diamond with the following note:
regards
Al
But given the issues with buffered port usage I do not see how this can be unless there is either a newer version of the code or I am missing something, perhaps Xmos can qualify this, is it possible to use the Square port in the interim perhaps?[12] Requires revised port assignment in application
regards
Al
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Confirmed yesterday that the supplied port mappings supplied by Marco work correctly with the Ethernet Slice on the USB Slicekit using the SQUARE slot:
PS: Be sure to modify the correct target hardware definition in the project (originally modified the L16 definition and wasted time till noting that the makefile is by default referencing the L2 target :(
Now the move to the use of the ALT DIAMOND is nasty work for the 4 bit PHY RX routine with the mix of inline and external assembler routines with limited documentation. A challenge to even locate the proper code flow but appears to be in the "reduced MII" routines.
PS: Be sure to modify the correct target hardware definition in the project (originally modified the L16 definition and wasted time till noting that the makefile is by default referencing the L2 target :(
Code: Select all
// Default to SQUARE
#define SMI_COMBINE_MDC_MDIO 1
#define SMI_MDC_BIT 0
#define SMI_MDIO_BIT 1
#define ETHERNET_DEFAULT_TILE tile[1]
#define PORT_ETH_RXCLK on tile[1]: XS1_PORT_1B
#define PORT_ETH_RXD on tile[1]: XS1_PORT_4A
#define PORT_ETH_TXD on tile[1]: XS1_PORT_4B
#define PORT_ETH_RXDV on tile[1]: XS1_PORT_1C
#define PORT_ETH_TXEN on tile[1]: XS1_PORT_1F
#define PORT_ETH_TXCLK on tile[1]: XS1_PORT_1G
#define PORT_ETH_MDIOC on tile[1]: XS1_PORT_4C
#define PORT_ETH_MDIOFAKE on tile[1]: XS1_PORT_8A
#define PORT_ETH_ERR on tile[1]: XS1_PORT_4D
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I must disappoint you, unfortunately. The Board U16 is not included in Ehternet board support. The translation will fail. Ask XMOS why it is not included. I have the U16 folder created in the project and with the on above-mentioned configuration on the square port to get to work.
greetings marco
greetings marco