XCore Exchange

Can anybody explain how this code can do 100M???

#pragma unsafe arrays
static uint32_t transfer32_sync_zero_clkblk(
out buffered port:32 sclk,
out buffered port:32 ?mosi,
in buffered port:32 ?miso,
uint32_t data, const unsigned period,
const unsigned cpol, const unsigned cpha){
unsigned time;
uint32_t d;
time = partout_timestamped(sclk, 1, cpol);
time += 100;

//bitrev the data
for(unsigned j=0;j<2;j++){
unsigned c = 0xaaaaaaaa>>(cpol ^ cpha);
for(unsigned i=0;i<16;i++){
partout_timed(sclk, 1, c, time);
if(!isnull(mosi)){
partout_timed(mosi, 1, data>>31, time);
data<<=1;
}
c>>=1;
time += period / 2;
partout_timed(sclk, 1, c, time);
c>>=1;
if(!isnull(miso)){
unsigned t;
miso @ time - 1 :> t;
d = (d<<1) + (t&1);
}
time += (period + 1)/2;
}
time += 80;
}
partout_timed(sclk, 1, cpol, time);
sync(sclk);
return d;
}

https://github.com/xmos/lib_spi

Features
SPI master and SPI slave modes.
Supports speed of up to 100 Mbit.
Multiple slave device support
All clock polarity and phase configurations supported.

Uh, take a look here: https://www.xmos.ai/download/lib_spi-[u ... .2rc1).pdf

The synchronous SPI master, which is what you're looking at, can't do anywhere near 100 Mbps. It's the asynchronous SPI master that can do 100 Mbps. Unfortunately the library documentation is for XS1 not XS2 so I don't know exactly what XS2 will do, but suffice it to say it's probably in the range of 20-30 Mbps.

Thanks akp, but this lib seems then be not very usable. As pdf say sync master Table 3 max speed around 3Mb is waste time with this lib.

Can you help me write simple 8 and 32 bit ( 32b continuos repeat too) for example 50Mbit speed. I need this for SPI LCD.

I am sorry, it's possible but you'll have to write it yourself. I have written 50 Mbps SPI master that's synchronous, but it took a lot of work in dual issue assembly and it was paid for by my employer. I don't have a method to open source it at present. To do it you'll need to use 32 bit buffered 1 bit ports, clock out the SPI clock like a 0xAAAAAAAA on one and clock out the SPI data on the other. For SPI LCD I suspect you don't need to read data back but it's the same process.

My result is too, that assembly is only way, that is source for my question, i read 100M but in code for async lib i see asm, that need explain

unsigned b = data>>7;
asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(XS1_CLKBLK_REF));
partout(mosi, 1, b);
asm volatile ("setclk res[%0], %1"::"r"(mosi), "r"(cb1));

I'm sorry, perhaps someone else will be able to explain XMOS assembly to you. But at the end of the day you'll have to learn it yourself to get the maximum performance you want. The way I do it is first write the code in C, then check the listing, and re-implement in assembly, then optimize. The document "xCORE-200: The XMOS XS2 Architecture" will be your friend. You must write it dual-issue to get ultimate performance and ensure the core is in high priority mode (100 MHz)

I today try start 25MHz SPI , but still have trouble

My init

stop_clock(cbspi);
configure_clock_rate(cbspi, 100, 4);
configure_out_port(SMOSI, cbspi, 0);
start_clock(cbspi);
asm volatile ("settw res[%0], %1"::"r"(SMOSI), "r"(8)); //8bit
clearbuf(SMOSI);
//spi mode 0
set_port_inv(SSCK);
partout(SSCK,1,1);
sync(SSCK);

and send 8 bit

SMOSI <: (bitrev(data)>>24);
SSCK <: 0xCCCCCCCC;

first send seems ok , but second no. What i miss?

Additional question how command i can use to handle end of FIFO transmision on buffered port?