I just want to share my efficient implementation of 64X decimation of 20MHz 1-bit Sigma-Delta data stream on xCORE-200.
Key features is:
- Only 4 CPU/thread cycles of latency (40 ns) between the last bit (of 64) are read on the port until the result is filtered and decimated, ready to be sent out to another thread over a streaming channel.
- A 768 tap FIR-filter (anti-alias ) can run at ~20MHz indata in just one thread. The taps can be chosen arbitrary, so minimum-phase filters can be used, for the highest possible closed-loop bandwidth
For use with isolated 20MHz 1 bit ADC chips, used for current measurements. No need for an extra dedicated ASIC or FPGA for deciamtion.
Asm, interrupts and LUT