I use 45M/49M MCLK Input in order to get 768k sample rate. I get BCLK for DEFAULT_FREQ when power on,but there is no LRCK output.
I only made below setting in customdefines.h.
#define MCLK_441 (1024*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (1024*48000) /* 48, 96 etc */
#define MAX_FREQ (768000)
By comparing with another board with 22.5792m/24.576m MCLK ,It can output LRCK normally.
LRCK no output under 45M/49M MCLK
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What IP are you referring to? If it's the USB reference design I don't know if it's possible. It's possible with lib_i2s with the i2s frame based master.
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My XU208 custom board.Let me check lib_i2s.
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Glad you got it fixed.
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Hello
What did you change to fix it ?
I have the MCLK at 24 MHz not 24.576 MHz....
Thanks in advance.
What did you change to fix it ?
I have the MCLK at 24 MHz not 24.576 MHz....
Thanks in advance.
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Are you saying your MCLK is "exactly" 24 MHz? What sample rate are you trying to generate? Typically the MCLK is some power of 2 multiple of your sample rate. E.g. 48 kHz * 2^9 = 24.576 MHz.
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Thanks for that fast reply. Yes the clock is exactly 24 MHz and i need a sample rate of 48 kHz. I tried to change the definition MCLK_48 to (500*48000) but then there is no more output (didn't know before that it has to be something with power of 2) ? Can the xmos generate or change that anyhow or do i have to change the oscilator ?
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It will be much easier if you use a 24.576 MHz oscillator. Are you interfacing with an ADC or DAC? If so, then the MCLK will have to be a power of 2 multiple of 48 kHz, typically 24.576 MHz or 12.288 MHz.
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So there is no way from software side to solve that ? I'm using a TLV320DAC3120, so dac. I have to change the oscillator or workarround with the ti amp, generate an output of 24.576 and input to the xmos ? Could be possible.