Integer clock cycle slip with AVB-DC + Mac Aggregate
Posted: Thu Mar 03, 2016 5:24 pm
Hello
I am observing integer clock cycle slip between my two AVB-DC boards from time to time. I am running them in a daisy chain and using the two as an aggregate 8 in / 8 out device with MacBook Pro running El Capitan. When they first come up they are synchronized; I am testing synchronization by putting the same sinusoid into both XA-SK-AUDIO-PLL boards and then recording to Audacity and viewing the zero crossings are coincident.
However, if I go away and come back and repeat the test, I can sometimes see integer cycle slips between the two boards. What I mean is, the zero crossing from one board will be delayed by an integer number of sampling periods vis-a-vis the other board.
I believe I have found part of the cause: when I view the LRCLK sync between the two boards on an oscilloscope, I have noticed that sometimes they will become unlocked and then repeat the locking process. If this happens, then the audio recorded on the MacBook will show the clock cycle slip issue. I can fix it by rebooting the MacBook.
Has anyone witnessed this behaviour and (if so) is there a good fix for it (other than rebooting the Mac)? I hope to extend this system to a much larger number of channels (boards) and I need to maintain synchronization to the (sub) clock cycle. Clock cycle slips will cause inaccuracies in the analysis we want to do on the recorded audio.
I have attached a screen shot showing the cycle slip, this was with a 1kHz sine wave put into both boards.
I am observing integer clock cycle slip between my two AVB-DC boards from time to time. I am running them in a daisy chain and using the two as an aggregate 8 in / 8 out device with MacBook Pro running El Capitan. When they first come up they are synchronized; I am testing synchronization by putting the same sinusoid into both XA-SK-AUDIO-PLL boards and then recording to Audacity and viewing the zero crossings are coincident.
However, if I go away and come back and repeat the test, I can sometimes see integer cycle slips between the two boards. What I mean is, the zero crossing from one board will be delayed by an integer number of sampling periods vis-a-vis the other board.
I believe I have found part of the cause: when I view the LRCLK sync between the two boards on an oscilloscope, I have noticed that sometimes they will become unlocked and then repeat the locking process. If this happens, then the audio recorded on the MacBook will show the clock cycle slip issue. I can fix it by rebooting the MacBook.
Has anyone witnessed this behaviour and (if so) is there a good fix for it (other than rebooting the Mac)? I hope to extend this system to a much larger number of channels (boards) and I need to maintain synchronization to the (sub) clock cycle. Clock cycle slips will cause inaccuracies in the analysis we want to do on the recorded audio.
I have attached a screen shot showing the cycle slip, this was with a 1kHz sine wave put into both boards.