opinions regarding proposed implementation etherernet+sdram
Posted: Wed Apr 21, 2010 3:14 am
I am trying to get the following implemented:
core 0 L1-128 with lan8700 for ethernet connection
5bit link
core zero link D to core 1 link C
core 1 L1-128 with sdram for huge FIFO
Boot scenario(s):
over jtag during development (xtag-2)
core 0 over spi boots core 1 over xlink
note second 2bit xlink for booting:
core 0 link A to core 1 link B
Some questions:
1. is booting core 1 via its link B probably workable?
2. Is the movement of the CS WE RAS and CAS from a 4 bit port to 4 1 bit ports likely to cause issue? It would be needed to free up port B for boot over xlink
3. Any issues mixing 2 bit and 5 bit links between 2 cores?
4. Are all 1 bit ports equal. I moved some bits from the XC-2 reference design to allow normal SPI boot, and am worried about clocks and buffered ports.
Any obvious errors (besides missing power and config?
Thanks in advance for any help. I will report on my results (making a simple server (not http just TCP) and attempting to move real-time data from xmos to a pc (QT application). I am hoping to get over 4Mbyte / s with around 1k packets. Data to be pushed from external 2bit link through core 1 where it is stored in memory. Data is pulled by core 0 from core 1 memory as fast as the ethernet will take it. Plan on using burst mode moving about 1k at a time.
Regards,
mike
core 0 L1-128 with lan8700 for ethernet connection
5bit link
core zero link D to core 1 link C
core 1 L1-128 with sdram for huge FIFO
Boot scenario(s):
over jtag during development (xtag-2)
core 0 over spi boots core 1 over xlink
note second 2bit xlink for booting:
core 0 link A to core 1 link B
Some questions:
1. is booting core 1 via its link B probably workable?
2. Is the movement of the CS WE RAS and CAS from a 4 bit port to 4 1 bit ports likely to cause issue? It would be needed to free up port B for boot over xlink
3. Any issues mixing 2 bit and 5 bit links between 2 cores?
4. Are all 1 bit ports equal. I moved some bits from the XC-2 reference design to allow normal SPI boot, and am worried about clocks and buffered ports.
Any obvious errors (besides missing power and config?
Thanks in advance for any help. I will report on my results (making a simple server (not http just TCP) and attempting to move real-time data from xmos to a pc (QT application). I am hoping to get over 4Mbyte / s with around 1k packets. Data to be pushed from external 2bit link through core 1 where it is stored in memory. Data is pulled by core 0 from core 1 memory as fast as the ethernet will take it. Plan on using burst mode moving about 1k at a time.
Regards,
mike