XK1 schematic and LS1 Booting procedures
Posted: Thu Dec 31, 2009 9:56 pm
I'd like to design my own XMOS L1 board and I'm reading through the XS1-L System Specification.
It says MODE3/MODE2 = 00 for JTAG and 11 for SPI boot.
On page 3 it says:
To boot from an SPI interface, an SPI slave device must be connected as follows.
Port Use
P1A0 SPI MISO
P1B0 SPI SS
P1C0 SPI SCLK
P1D0 SPI MOSI
However, on the XK1 schematic, it shows the SPI flash ram connected to:
XD36 P1M0 PORT_SPI_MISO
XD37 P1N0 PORT_SPI_SS
XD38 P1O0 PORT_SPI_CLK
XD39 P1P0 PORT_SPI_MOSI
1) What is the difference here and how does the XK1 able to boot from the SPI FLASH when it is connected on a different port?
2) I noticed the L1_64TQFP reference example has JP1 on Mode2/Mode3 to optionally connect to GND or otherwise left floating. On the XK1 schematic, Mode2/Mode3 are tied to TRST_N_BUF.
Does the MODE2/MODE3 pins have internal pullups and it is sufficient to tie them to TRST_N_BUF so that an XTAG2 will put it into JTAG mode when it needs to be and otherwise just boots normally from the SPI flash? It is ok to do this without the NC7WZ17 buffer or pullup resistors on Mode2/Mode3?
3) The L1_64TQFP reference design and the XTAG2 design have a power on reset chip NCP303LSN09 that holds RST_N high. The L1_64TQFP ref design also has a NC7WZ07 which holds TRST_N high at boot.
However, the XK1 doesn't have any of these chips. From my understanding the NCP303LSN09 just holds the RST_N high until the 1V has stabilized and is energy efficient.
Looking at Omer's Stamp breakout board: http://www.xcore.com/projects/xs1-l1-64-stamp-breakout
A .1uf cap + 2.2k resistor is used to provide a delay in the booting. This would save some costs and board complexity.
Has anyone tried it?
It says MODE3/MODE2 = 00 for JTAG and 11 for SPI boot.
On page 3 it says:
To boot from an SPI interface, an SPI slave device must be connected as follows.
Port Use
P1A0 SPI MISO
P1B0 SPI SS
P1C0 SPI SCLK
P1D0 SPI MOSI
However, on the XK1 schematic, it shows the SPI flash ram connected to:
XD36 P1M0 PORT_SPI_MISO
XD37 P1N0 PORT_SPI_SS
XD38 P1O0 PORT_SPI_CLK
XD39 P1P0 PORT_SPI_MOSI
1) What is the difference here and how does the XK1 able to boot from the SPI FLASH when it is connected on a different port?
2) I noticed the L1_64TQFP reference example has JP1 on Mode2/Mode3 to optionally connect to GND or otherwise left floating. On the XK1 schematic, Mode2/Mode3 are tied to TRST_N_BUF.
Does the MODE2/MODE3 pins have internal pullups and it is sufficient to tie them to TRST_N_BUF so that an XTAG2 will put it into JTAG mode when it needs to be and otherwise just boots normally from the SPI flash? It is ok to do this without the NC7WZ17 buffer or pullup resistors on Mode2/Mode3?
3) The L1_64TQFP reference design and the XTAG2 design have a power on reset chip NCP303LSN09 that holds RST_N high. The L1_64TQFP ref design also has a NC7WZ07 which holds TRST_N high at boot.
However, the XK1 doesn't have any of these chips. From my understanding the NCP303LSN09 just holds the RST_N high until the 1V has stabilized and is energy efficient.
Looking at Omer's Stamp breakout board: http://www.xcore.com/projects/xs1-l1-64-stamp-breakout
A .1uf cap + 2.2k resistor is used to provide a delay in the booting. This would save some costs and board complexity.
Has anyone tried it?