Getting Started with the StarterKit

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IraqiGeek
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Post by IraqiGeek »

pstnotpd wrote: Good work!!

I'm not an experiended user I suppose, but still...
Thanks! Really appreciated :)

I am learning about the XCore myself and writing these posts as I go :)
pstnotpd wrote: You might want to add a short explanation how the new "Tile" naming convention relates to the "Xcore" convention used in the original document. I.e. Tile==Xcore (or so I believe).
Tile and core lack a clear distinction in the documentation. My understanding is that a tile is the physical processor, complete with its 8 XCore threads, memory, I/O and resources. An 8 thread chip is one tile, while a 16 thread chip is two tiles.

Anyone from the XCore team want to chime in on this?
pstnotpd wrote: Also, with the XC2 specification I believe it is possible to do a kind of "soft threading" with the combinable and distributable task feature. The architecture document only mentions hardware threads.
I'm trying to limit my posts to the scope of the StarterKit intentionally. My main objective is to hopefully create a series of simplified tutorials to help newbies like myself get off the ground and get their training wheels off.

Still, if you have any reference to any documents I haven't mentioned in this thread, or newer versions of the ones I did, I'd greatly appreciate it.
pstnotpd wrote: It's all very confusing for newbies and my personal main gripe with the current state of documentation.
Agreed. This continues to be my biggest gripe. Most of the documents I've found have been through Google, as even the links within the documents can't be trusted.

For example, the old Programming guide, X9577A, is the one I found referenced in other documents. But this has been superseded by X1009B (which I found by complete accident also through Google). However, the new one omits Appendix B which provides a lot of helpful code examples in various port configurations and Appendix C which provides a nice, cheat sheet sort documentation for xs1.h (I know xs1.h is pretty well documented, but this provides a nice quick reference for the most used functions). Ditto for the secion explaining port to pin mappings.


richard
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Post by richard »

markey1979 wrote:I think the hardware manual is also incorrect on page 9. I think the port and pin numbers should be reversed. It is just a little confusing because everywhere else in the document the naming convection's are reversed.

.... But I am new to this also. I could be totally wrong.
You are quite right. I've passed this information on so the document can be fixed.
richard
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Post by richard »

segher wrote:Buffered ports can use any (positive ;-) ) multiple of the
port width as transfer width, with a maximum of 32 bits.
You usually use either the port width or 32, whichever is
most convenient or most efficient, but other things work
as well. You can also do partial transfers to handle leftovers.
Actually you can only set the transfer width to certain values. You can always set the transfer width to the port width. In addition you can set it to any of the widths (4, 8, 32) so long as the transfer width is a multiple of the port width. This is documented in the XS1 Ports Introduction document.

If you want to transfer data to / from the port at a different width you can set the transfer width to a higher number and use partial inputs and outputs to send and receive data.
richard
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Post by richard »

IraqiGeek wrote:I hope the moderators of this forum, and the people at XMos don't take my comments above as criticism. The XCore StarterKit is an amazingly priced, amazingly powerful little board. Even in single threaded operation it is more powerful than most hobbyist ARM boards, and easily an order of magnitude more powerful than AVRs.
There is some excellent constructive feedback here - thanks for taking the time to collect this information together. Your blog posts look great as well.
IraqiGeek wrote:Tile and core lack a clear distinction in the documentation. My understanding is that a tile is the physical processor, complete with its 8 XCore threads, memory, I/O and resources. An 8 thread chip is one tile, while a 16 thread chip is two tiles.

Anyone from the XCore team want to chime in on this?
A tile contains up to 8 logical cores, memory, I/O and resources. At one point the terminology changed, so you might see old documents refering to threads instead of logical cores. These terms both refer to the same thing.
IraqiGeek wrote:
pstnotpd wrote: Also, with the XC2 specification I believe it is possible to do a kind of "soft threading" with the combinable and distributable task feature. The architecture document only mentions hardware threads.
I'm trying to limit my posts to the scope of the StarterKit intentionally. My main objective is to hopefully create a series of simplified tutorials to help newbies like myself get off the ground and get their training wheels off.

Still, if you have any reference to any documents I haven't mentioned in this thread, or newer versions of the ones I did, I'd greatly appreciate it.
The document XMOS Multicore Extensions to C describes interfaces in xC and how to use them to combine several tasks onto the same logical core. I would definitely recommend reading it if you haven't already.
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segher
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Post by segher »

richard wrote:Actually you can only set the transfer width to certain values. You can always set the transfer width to the port width. In addition you can set it to any of the widths (4, 8, 32) so long as the transfer width is a multiple of the port width.
That's not what the architecture book says. Is it wrong?
I'm too lazy to actually try it out right now, sorry :-)
IraqiGeek
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Post by IraqiGeek »

richard wrote:
Actually you can only set the transfer width to certain values. You can always set the transfer width to the port width. In addition you can set it to any of the widths (4, 8, 32) so long as the transfer width is a multiple of the port width. This is documented in the XS1 Ports Introduction document.

If you want to transfer data to / from the port at a different width you can set the transfer width to a higher number and use partial inputs and outputs to send and receive data.
Thanks for the Ports doc link :)

Can you please clarify a bit the transfer width? First, its the transfer size, right? And second, on a 1-bit port, does that mean I can set the transfer width/size to any number of bits? Say, 9 bits? This is especially useful with SPI and I2C devices.
Last edited by IraqiGeek on Sat Jan 04, 2014 2:28 am, edited 1 time in total.
IraqiGeek
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Post by IraqiGeek »

richard wrote: There is some excellent constructive feedback here - thanks for taking the time to collect this information together. Your blog posts look great as well.
Thanks and thanks :)
richard wrote: A tile contains up to 8 logical cores, memory, I/O and resources. At one point the terminology changed, so you might see old documents refering to threads instead of logical cores. These terms both refer to the same thing.
Thanks for confirming this. I'll check my blog posts and update them as necessary to unify naming convention.
richard wrote: The document XMOS Multicore Extensions to C describes interfaces in xC and how to use them to combine several tasks onto the same logical core. I would definitely recommend reading it if you haven't already.
Thats exactly what I was looking for! I knew there was a document somewhere that listed that :)

IMHO, document like the C-Extensions, the programming guide, XS1 architecture, and the intro to ports need to be prominently listed on the StarterKit microsite, and also be linked to in the StarterKit getting started document.

The C-Extensions looks like it will be a newbie's best friend once we wrap our heads around the hardware.

Does XC support high level exception handling? Something like try-catch-finally? global exception handlers? Any document(s) that explain/detail this?

The programming guide talks about exceptions in the context of the instruction set, but nothing about how to handle them in XC.

Thanks again :)
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Bianco
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Post by Bianco »

There is no exception handling in XC. Unlike exceptions in high languages, an exception caused by an instruction is usually an unrecoverable error. The logical core will jump to a place in memory that is the KEP (kernel entry point). You could place your own exception handler there and determine whether the system can continue or not, but this would require writing some assembly.
IraqiGeek
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Post by IraqiGeek »

Section 3.12, "How to dynamically change the type of a port" at the end of XMOS Multicore Extensions to C (last two pages, 59-60) is missing the example showing how to reconfigure a port. Its also missing from the web version of the document.
richard
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Post by richard »

IraqiGeek wrote:Section 3.12, "How to dynamically change the type of a port" at the end of XMOS Multicore Extensions to C (last two pages, 59-60) is missing the example showing how to reconfigure a port. Its also missing from the web version of the document.
I'm not sure what you mean - the documentation has the code needed to reconfigure the port inline with the text. You can get the complete example by concaternating all the code in this section.

Usually the examples are also available from the HowTo tab of the xTIMEcomposer. However in this case the example isn't available yet (it's in a queue to be published). For now I've posted the complete example below:

Code: Select all

#include <xs1.h>

out port p = XS1_PORT_1A;

int main() {
  out port * movable pp = &p;
  buffered out port:32 * movable buffered_p;

  buffered_p = reconfigure_port(move(pp), buffered out port:32);
  *buffered_p <: 0xa0a0a0a0;
  pp = reconfigure_port(move(buffered_p), out port);

  return 0;
}
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