What's all this RISC-V stuff, anyhow?

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
User avatar
fabriceo
Experienced Member
Posts: 70
Joined: Mon Jan 08, 2018 4:14 pm

Post by fabriceo »

Hi, Thank you for the links. Very instructive. Seems each tile will embody an ALU with FP and Vector unit as in the XS3A, let see if they also introduce additional instruction in RV32IM like the 32x32=64 MACC or LSAT or Lextract on 64 bits dual registers.
Also they have hacked the 32bit encoding instruction so that 2x16 bits instructions can be encoded and executed in parallel. let see in practice how the M/R/M+R/M&R actual constrains are handled in the risc-v world.

What is still not clear to me is how the xcore specificities related to hardware threads (aka HARTS now) and the event based model (instead of usual interrupt) will be formalized in the risc toolsets, as the XC compiler and language would be discontinued. Also the concept of "interface" which simplifies inter-tile communication is "lost in translation". No words on the target software framework during the presentation.
Last edited by fabriceo on Wed Jan 18, 2023 10:17 am, edited 2 times in total.


User avatar
akp
XCore Expert
Posts: 570
Joined: Thu Nov 26, 2015 11:47 pm

Post by akp »

I hope it works out but honestly I am a little confused as to the value proposition. It seems like a lot of new additions to the ISA just to get back to about where they're already at with XS3? So that means XMOS is also doing a lot of work on a RISC-V compiler to get it to optimally generate the new instructions? Maybe I just don't understand RISC-V but I don't really see what RISC-V is bringing to the table. And it seems like we'll still need to have a pretty deep understanding of tiles (or cores, whatever they're called now) to know the best way to communicate between HARTS, if they can share memory, etc.

Answers some questions but raises more I would say. I honestly have a lot invested in XC and the XS2 ISA so I just hope that toolchain support will continue for a while. I don't want to rewrite code that I spent many years getting to the point of reliability and capability.
User avatar
aclassifier
Respected Member
Posts: 445
Joined: Wed Apr 25, 2012 8:52 pm

Post by aclassifier »

I have tried to make the theme personal here. From there:

I don’t know how much work it has been to implement the X4, provided you have the X3 with a proprietary instruction set. I guess this to some degree is dependent on whether the X1-X3 is microcoded and if the X4 is so – whether XMOS has gone for a microcoded RISC-V. It looks like the latter is possible (here). I didn’t think the present processors were microcoded. Then going from one microcoded architecture to another one would be less of a chore than any other alternative, I assume? Assuming they haven’t thrown (too m)any babies out with the bathwater?

Any comments?
--
Øyvind Teig
Trondheim (Norway)
https://www.teigfam.net/oyvind/home/
User avatar
aclassifier
Respected Member
Posts: 445
Joined: Wed Apr 25, 2012 8:52 pm

Post by aclassifier »

CousinItt wrote: Mon Jan 09, 2023 2:05 pm Back to RISC-V...

Recent interview with Mark Lippett, XMOS CEO on this topic.

https://edacafe.com/video/XMOS-Mark-Lip ... media.html
How do we read Mark Lippett's statement that "We have never claimed binary compatibility, we've always asked our customers to recompile their code, that will remain the case as we move from an xcore instruction set to a RISC-V instruction set".

May this indicate that they will indeed port the xC compiler? Or does he disregard the years of xC completely?
--
Øyvind Teig
Trondheim (Norway)
https://www.teigfam.net/oyvind/home/