What's all this RISC-V stuff, anyhow?

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
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CousinItt
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What's all this RISC-V stuff, anyhow?

Post by CousinItt »

Hi all,

you may have seen the recent announcements about the fourth generation of xmos processors using RISC-V. I thought I'd kick off a thread to discuss this news and for any updates. Feel free to chip in.

There are some links below. You can get the white paper if you enter some details, but it doesn't give away much. There was also a presentation at the RISC-V summit last week but I've not been able to find a copy.

To me this announcement makes some sense. The RV32IM instruction set is very efficient - performance and die areas shouldn't suffer. It's also well supported by tools, and we know what an "interesting" time xmos has had with tools lately.

I assume some special instructions will be added to support xconnect channels, ports, timers etc.

My main concern is how well these new devices will support DSP. The M extension includes multiplication, but you can only access the high word or the low word of the result. A single-cycle signed 32x32=64 integer multiplication with saturation is a must-have for me. I'd also like to see on-board ethernet as in the XE-216. Of course it won't matter too much if they are going to continue making XCORE-200/300 devices with USB/ethernet.

What would you look for in these devices?

Merry Xmos to all!


https://www.xmos.ai/using-risc-v-to-def ... -software/

https://www.xmos.ai/xmos-announces-soft ... th-risc-v/

https://www.xmos.ai/xcore-and-risc-v-a-major-milestone/


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akp
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Post by akp »

I will be interested to read the documentation.

Honestly I won't be switching right away because of all the IP I've generated for XS2A that already works using a mix of XC, C, and assembly. I know XC is dead, but I have a lot of XC I use. Likewise, I've written a fair bit of assembly for XCORE-200, mostly to make better use of dual-issue than the compiler can do. I wonder if some features I used won't be available. On the other hand, perhaps there are features in the RISC-V ISA that are better than XS2A / XS3A.

At the end of the day I don't think I am the target customer for this. If XCORE-200 goes away I am not sure what I will do.
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fabriceo
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Post by fabriceo »

Hi
this is a valid subject. for some years we see XMOS moving in different direction probably to catchup some business opportunity as driving a company is not only a question of technology...

after the massive effort for delivering a very interesting solution with XS2 architecture (multicore, event driven, fast instructions, dual lane, great instructions like maccs,lsat,crc...) and all the specific langage concept (XC) to make this possible, there were some changes:
- introduction of freertos since the Voice products, which is somehow conflicting with inherent scheduler capacities. Of course we may need more thread but then cooperative scheduling is easy to implement in a "select default" (https://www.xcore.com/viewtopic.php?t=7272)
- introduction of FPU and vector solution for AI device and IOT (the devkit includes a wifi device). This type of device doesn't require the specific port buffering and clocking or even a fast event driven programing, but instead would require easy solution to connect to other peripherals (sensor,i2s,spi) which are still to be done in software...
- introduction of a new toolchain and SDK without official compatibility with Eclipse xTimeComposer (but we are lucky, this works immediately by copy pasting the 15.x toolchain folders in the eclipse application folder)
- stopping devolvement around XC langage but still XC is the only good solution to do multitasking, even driven programing, and to handle automatically complex interfaces. doing that with the proposed lib_xcore is boring.
- now announcing RISC-V but the XCORE ISA is already very optimized for 16 and 32bits instructions...

anyway, lets trust the company strategy, at least they demonstrated their ability to deliver massives solutions and tools and documentation !

cheers, good luck, happy 2023
AndyCap
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Post by AndyCap »

fabriceo wrote: Wed Dec 21, 2022 3:29 pm ...
- introduction of a new toolchain and SDK without official compatibility with Eclipse xTimeComposer (but we are lucky, this works immediately by copy pasting the 15.x toolchain folders in the eclipse application folder)
...
Hi Fabriceo,

Do you have any details of how to get this to work, I have it (and a few other things) and all I get is an xTimeComposer that doesn't start.

Any help would be really appreciated.

Many Thanks

Andy
AndyCap
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Post by AndyCap »

AndyCap wrote: Thu Dec 22, 2022 11:05 am
fabriceo wrote: Wed Dec 21, 2022 3:29 pm ...
- introduction of a new toolchain and SDK without official compatibility with Eclipse xTimeComposer (but we are lucky, this works immediately by copy pasting the 15.x toolchain folders in the eclipse application folder)
...
Hi Fabriceo,

Do you have any details of how to get this to work, I have it (and a few other things) and all I get is an xTimeComposer that doesn't start.

Any help would be really appreciated.

Many Thanks

Andy
Don't worry, I have it going now.

Cheers

Andy
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CousinItt
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Post by CousinItt »

Back to RISC-V...

Recent interview with Mark Lippett, XMOS CEO on this topic.

https://edacafe.com/video/XMOS-Mark-Lip ... media.html
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CousinItt
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Post by CousinItt »

Mark Lippett's presentation to the RISC-V conference last month.

https://www.youtube.com/watch?app=desktop&v=WBfZK3EWPAs
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akp
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Post by akp »

It would be interesting to see Henk's presentation that Lippett referred to at the end of his talk.
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CousinItt
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Post by CousinItt »

As requested, here's Henk Muller's presentation...

https://www.youtube.com/watch?v=q594f_7Irg0
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Post by CousinItt »

It's encouraging that they are supporting a dual issue capability similar to the xcore 200/300, but I wished he'd said a bit more about DSP operations.