Unclear datasheet - OTP/external boot pin

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
bonelli
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Posts: 8
Joined: Wed Feb 03, 2021 9:06 pm

Unclear datasheet - OTP/external boot pin

Post by bonelli »

Hello,

The datasheet of XE216 mentions:
The xCORE Tile boot procedure is illustrated in Figure 8. If bit 5 of the security
register (see §9.1) is set, the device boots from OTP. To get a high value, a 3K3
pull-up resistor should be strapped onto the pin. To assure a low value, a pull-down
resistor is required if other external devices are connected to this port
.
So, the question is: where is this pin ? They is nothing about it on the datasheet, and no pull-up in the ref design schematics.


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CousinItt
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Joined: Wed May 31, 2017 6:55 pm

Post by CousinItt »

The language used in the data sheet is a little sloppy. "The pin", in this case, refers to X0D06, X0D05 and X0D04 as shown in Figure 9. To set a 1 value, pull up to VDDIO with a 3k3; to set a 0, just leave the port open. If something else is also connected to any of those pins, you will need to take its effects into account to guarantee the pin state. That's what the text you highlighted is saying.

In the explorer kit, the only thing connected to the boot source pins is the QSPI flash, which has negligible leakage which is overcome by the internal pull-downs on those pins. Note the pull-up on X0D01, the chip select for the QSPI flash, ensures the chip is disabled during the time the boot source pins are read.
bonelli
Member
Posts: 8
Joined: Wed Feb 03, 2021 9:06 pm

Post by bonelli »

ok. I'm using the same flash device and connection than the explorer kit, so, I should works fine.
Thank you CousinItt :)