new - more details?

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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new - more details?

Postby ozel » Tue Mar 24, 2020 3:58 pm


since there's still no thread about the new chip generation, I felt an urge to start this. :-)
From the tech. white paper it looks like we could be getting minimum 2 cores running with 800 MHz each, that'd be amazing!

I've got two burning chip package questions since I'm designing new boards right now:
Will there be a package that is pin-compatible one of the previous xcore-200 chips, if so which one?
If not pin compatible, would still be offered in a TQFP package? (Pretty please 'yes'! :)

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Postby akp » Fri Mar 27, 2020 1:51 pm

I'm pretty stoked about the FPU and the vector unit, but I would like the RGMII too. I know that's not the focus of this part but it would be pretty cool for my application, which uses DSP and Ethernet but not AI.
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Postby Redeye » Mon Mar 30, 2020 9:45 am

This does look interesting. For me the vector arithmetic part looks especially interesting as it can probably be used for big FIR filters which the current architecture isn't great for. Not too bothered about package, as long as it's not that TQFN package again - that would be a dealbreaker because it was a nightmare to work with.
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Postby akp » Wed Apr 01, 2020 9:38 pm

Any idea if we're limited to same number of chanends and cores per tile as in XS1 and XS2?

Edit: it looks like we're limited to 8 cores still. I think with the new FreeRTOS SOC framework XMOS is working on it would be beneficial to have more cores and chanends, and use the low priority cores to form the interfaces we need between XC cores (peripherals) and FreeRTOS core(s).
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Postby ozel » Fri Apr 03, 2020 8:09 pm

yeah, though it seems this time every logical core of max. 8 per tile (I love that they’ve reintroduced the old hardware thread term ;) would be able to get 100 MHz and run with up to 200 Mips in dual-issue mode
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Postby TSC » Thu Jun 04, 2020 12:59 am

Some news!

Insightful analysis of from The Linley Group

tinyML Talks Webcast: Low-cost neural network inferencing on the edge with

It looks like the new parts are still undergoing final tweaks and testing.
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Postby kevpatt » Sun Jun 14, 2020 12:59 am

In the Linley report it seems to indicate the chip has 4 xCONNECT links, which would enable scalability well beyond two chips. That would be huge.
Any idea if these links are compatible with xCORE-200 links? That would enable use of an xCORE-200 co-processor to host RGMII, additional USB, or lots of additional GPIO... I would assume so, as it seems XS3 is a natural evolution from XS2 and the internal architecture seems about the same (plus the Vector and FP capability).

This is an incredible development. Way to go XMOS!
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Postby RitchRock » Tue Aug 04, 2020 8:46 pm

From the latest product brief it looks like the chip will come in 7x7mm, 60-pin QFN 0.4mm pitch and 14x14mm, 265-pin BGA 0.8mm pitch. I'm about to start a new design and am considering to again use XE/XU216, but not sure if I should wait to see exactly what the new offerings will be. Hopefully we see the chips / cost / development tools soon!
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Postby darek » Thu Oct 29, 2020 1:22 pm

Hi All,
any updates on the cpu+ dev kit availability?

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Postby CousinItt » Mon Nov 02, 2020 12:01 pm

Pages for XU316-1024-FB265 and XU316-1024-QF60A datasheets have appeared on the site, but the links are dead. Both are dated 1 Sept 2020, and the revisions are 22 and 18 respectively. I don't know if that is a good sign.

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