New XMOS chips??!

[segher]

I love those tidbits, great way to keep interest until real
documentation is ready :-)

You can specify up to 4 priority cores

Is this really true, i.e. does it enforce this limit? If not, what
happens? In the simplest possible implementation the low
priority threads will be starved?

[Hagrid]

Have you tried to contact XMOS sales directly?

No response from XMOS sales. Pinged them again today.

[Hagrid]

Further random xCORE-200 trivia: the scheduler now has a priority mode. You can specify up to 4 priority cores, each of which will get 1/5th of the core speed (ie scheduled as quickly as possible with 5 stage pipeline). All other cores get a share of the remainder.

Example:

Logical core 0,1 - 100MHz each
Logical cores 2..7 - 50MHz each

Just been working through the datasheet for XU216-512-TQ128. Figure 3 shows minimum 63 MIPS for 8 cores with the comment "There is no way that the performance of a logical core can be reduced below these predicted levels."

If I understand this right, with 4 priority cores, the minimum MIPS on the remaining 4 cores would be minimum 25 MIPS.

XMOS might want to put a footnote in there somewhere...

[infiniteimprobability]

If I understand this right, with 4 priority cores, the minimum MIPS on the remaining 4 cores would be minimum 25 MIPS.

You are correct!

XMOS might want to put a footnote in there somewhere...

I just checked the datasheet - it doesn't even mention priority.. I'll add a bug against the datasheet. Thanks for the catch..

[infiniteimprobability]

Is this really true, i.e. does it enforce this limit? If not, what
happens? In the simplest possible implementation the low
priority threads will be starved?

It's not enforced ... so you can enable more than 4, but here be dragons and it can get a bit weird!!

The low priority group will be scheduled at least every 5 slots, and the members of group will round robin within that.
So in the case of 7 priority and 1 normal, you'll get priority inversion.

Eg.

P0, P1, P2, P3, L5, P4, P5, P6, P0, L5, P1, P2, P3, P4, L5 etc..

So the normal thread will get 500/1 = 100MHz and the others will get 400/7 = 57.14MHz

Note. MHz as MIPs is starting to get a bit inaccurate now..

[segher]

Ooh, interesting! [I _still_ haven't figured out how the
scheduler really works, not on L/G either ;-) ]

So, priority threads can never starve normal threads
completely, and as long as you have at most four priority
threads running, each of those will be scheduled every
fifth cycle. It also seems that the normal threads are
scheduled just as they were on L/G (if a slot isn't taken by
a priority thread).

But what if, say, there are five priority threads running and
no normal threads? Is the fifth slot still reserved for normal
threads?

Re: MIPS vs. MHz: Let's call them "VLIW MIPS", that will
certainly make things clearer, har har. But marketing will
not like it :-P

[infiniteimprobability]

But what if, say, there are five priority threads running and
no normal threads? Is the fifth slot still reserved for normal
threads?

No - the normal priority slot is not reserved if there is nothing in the normal priority run set. So you get 5 threads at 100MHz each, exactly the same as if you had 5 normal threads.

[Hagrid]

I started looking at the XL216-512-TQ128 and did a footprint for it in my favourite PCB software.

Then realised I could possible need a USB port, so "upgraded" to the XU216-512-TQ128. Hmm - trap there.

As the explorerkit uses the XE216-512-TQ128, I had a look at that chip as well.

According to the relevant datasheets, the pinouts on the XU and XE chips are identical (subject to rechecking). However, the XL chip is vastly different - only 22 pins retain their function between the XL and the XU/XE chips.

Is this for real? Or is it a "preliminary datasheet oops"?