XS1-U8A with VSUP = 3.3 V

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
Post Reply
User avatar
jjlm98
Member++
Posts: 31
Joined: Tue Aug 26, 2014 11:00 pm

XS1-U8A with VSUP = 3.3 V

Post by jjlm98 »

Hi all - just a few quick questions when operating the XS1-U8A with the VSUP supply held at 3.3 V and not 5.0 V:

1) Are there any requirements when operating the device with VSUP held at 3.3 V (configuration pin as on some FPGAs, etc.), or is tying VSUP to a 3.3 V supply simply enough?

2) Page 23 of the data sheet states that all supplies most be brought up monotonically. Does this mean I cannot tie the VSUP and VDDIO supplies together from the same supply when operating in 3.3-V mode? Do they need to be sequenced in any special fashion? Can I not simply relax this requirement and tie the two together?

3) The data sheet implies that running VSUP at 3.3 V reduces efficiency - has this been quantified in any fashion?

4) In 3.3-V mode, no 5-volt supply is present. The data sheet states the USB_VBUS pin must be connected, but this seems like an ESD diode forward-bias hazard. Can the USB_VBUS pin tolerate VBUS-level voltages, or must there be a divider between the raw VBUS supply and the USB_VBUS pin?

Thanks in advance.


User avatar
infiniteimprobability
XCore Legend
Posts: 1126
Joined: Thu May 27, 2010 10:08 am
Contact:

Post by infiniteimprobability »

1) Are there any requirements when operating the device with VSUP held at 3.3 V (configuration pin as on some FPGAs, etc.), or is tying VSUP to a 3.3 V supply simply enough?
VSUP (and VDDIO of course) to 3v3 is all you need. The U-series device handles all of the power sequencing for you.
2) Page 23 of the data sheet states that all supplies most be brought up monotonically. Does this mean I cannot tie the VSUP and VDDIO supplies together from the same supply when operating in 3.3-V mode? Do they need to be sequenced in any special fashion? Can I not simply relax this requirement and tie the two together?
Tie together is fine. There are various delays that happen (see 14.3) that occur whilst the supplies settle (come within tolerance) and reset delay etc. Part of the power sequence is the chip switching on VDDIO internally (via a beefy on-chip FET) anyhow. So the VDDIO supply is also controlled internally.
So yes, tie the two together and just apply the volts in a nice (monotonic) manner!
3) The data sheet implies that running VSUP at 3.3 V reduces efficiency - has this been quantified in any fashion?
Hmm, well from our measurements, having a smaller voltage difference between in/out is a smidge more efficient. I have see around 10-15mW better efficiency when running from 3v3 rather than 5v0. However, if the 3v3 is derived from 5v0 anyhow, then it is almost definitely going to be more efficient overall to have a single stage DC-DC of 5v0 to 1v0 inside the chip, rather than cascading two lots of inefficiencies 5v0 -> 3v3 (external DC-DC) with 3v3 -> 1v0 (DC-DC inside our chip)
4) In 3.3-V mode, no 5-volt supply is present. The data sheet states the USB_VBUS pin must be connected, but this seems like an ESD diode forward-bias hazard. Can the USB_VBUS pin tolerate VBUS-level voltages, or must there be a divider between the raw VBUS supply and the USB_VBUS pin?
Yes this is fine. The VBUS pin is actually just a set of comparators for detecting valid VBUS ranges against an internal reference, so a potential divider would upset the thresholds and you may not be able to detect valid VBUS (which is require for self powered operation - VBUS level is don't care for bus powered operation, because if you are on, so must VBUS be).
User avatar
jjlm98
Member++
Posts: 31
Joined: Tue Aug 26, 2014 11:00 pm

Post by jjlm98 »

Thank you so much for the detailed responses. I was confusing the term "monotonic" with "one after the other" but after your clarification it's clear it simply refers to a smooth upward-bound supply bring-up.

I'll post back if I have any more questions. Cheers!
Post Reply