What the hell is PORT_MCLK_COUNT ?

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bonelli
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Posts: 8
Joined: Wed Feb 03, 2021 9:06 pm

What the hell is PORT_MCLK_COUNT ?

Post by bonelli »

Hello,

I've been looking for a too long time for the signification, usage, purpose of PORT_MCLK_COUNT located in the xn file. This is located on a 16-bit port, overlapping with ethernet.

Obviously, removing the definition in the xn file makes the build fail.

There is no trace of test point in any schematics. Nothing in the documentation, nothing on the forum. Just a line in main.xc:

Code: Select all

        /* USB Packet buffering Core */
        {
            unsigned x;
            thread_speed();

            /* Attach mclk count port to mclk clock-block (for feedback) */
            //set_port_clock(p_for_mclk_count, clk_audio_mclk);
#if(AUDIO_IO_TILE != XUD_TILE)
            set_clock_src(clk_audio_mclk2, p_mclk_in2);
            set_port_clock(p_for_mclk_count, clk_audio_mclk2);
            start_clock(clk_audio_mclk2);
#else
            /* Uses same clock-block as I2S */
            asm("ldw %0, dp[clk_audio_mclk]":"=r"(x));
            asm("setclk res[%0], %1"::"r"(p_for_mclk_count), "r"(x));
#endif
Does someone have information on this port?


RitchRock
XCore Addict
Posts: 180
Joined: Tue Jan 17, 2017 9:25 pm

Post by RitchRock »

Here is what I think -
1. The line you posted as you probably know is attaching clk_audio_mclk2 to the port in question. What this means is the edges of the clock are used to sample and output data.
2. Below on line ~440 in main() this port definition is also passed into buffer().
3. In buffer() on line 407 there is some assembly that "gets MCLK count". Without diving too deep here it looks like it is then used as feedback to sync up the start of frame.
4. If there is OPT_RX or COAX_RX (port 16b on tile one) then the clock is probably used to sample this data based on the edge of the MCLK. Note that I got this from : https://www.google.com/url?sa=t&rct=j&q ... kRrnMRNf62

Not completely positive on this, but might give a little more light.
bonelli
Member
Posts: 8
Joined: Wed Feb 03, 2021 9:06 pm

Post by bonelli »

Your file seems to be broken. Is it this one https://www.xmos.ai/file/xcore-200-devi ... ion=latest Or a more detailed one ?

4: Effectively, OPT_RX and COAX_RX (X1D38/39, 1B ports, not 16B) are shared with the 16B port PORT_MCLK_COUNT (as well as MIDI and ETH). And it is a 16 bit input port clocked by MCLK.

Not clear about what PORT_MCLK_COUNT is counting : it's clocked by MCLK, registering ETH, MIDI I/O, ADAT input and SPDIF input ... although software documentation is about feedback and USB SOF. One more kind of magic.
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fabriceo
Experienced Member
Posts: 64
Joined: Mon Jan 08, 2018 4:14 pm

Post by fabriceo »

hi Bonelli,
each port as a 16 bit counter that can be read with the getts assembly instruction.
as such the 16bits port PORT_MCLK_COUNT is never used , this is a trick to be able to access its ts counter without allocating a formal 1bit port.
This is used in SOF (usbbuffer.xc) to measure how much mclk tick happened during 2 USB frame (125us).
With this information the application returns the frequency of the device to the host in the feedback endpoint, relatively to the host 8khz timebase.
Clock feedback to the host is one of the most tricky part of this application :)
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Fabien
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Posts: 11
Joined: Fri Mar 09, 2018 4:16 pm

Post by Fabien »

fabriceo wrote: Sat Dec 10, 2022 5:21 pm hi Bonelli,
each port as a 16 bit counter that can be read with the getts assembly instruction.
as such the 16bits port PORT_MCLK_COUNT is never used , this is a trick to be able to access its ts counter without allocating a formal 1bit port.
This is used in SOF (usbbuffer.xc) to measure how much mclk tick happened during 2 USB frame (125us).
With this information the application returns the frequency of the device to the host in the feedback endpoint, relatively to the host 8khz timebase.
Clock feedback to the host is one of the most tricky part of this application :)
Great explanation, I have been wondering the same thing for a while! Thank you!