One led per core/thread

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segher
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Re: One led per core/thread

Postby segher » Sat Dec 28, 2013 2:41 pm

Hi again,

You have OUTCT and CHKCT swapped: you have a channel
from the slave to the master, and not in the other direction,
so that is the one you need to close. But your code isn't
getting that far yet...

You don't need to use events here: every thread is waiting
for something to happen on only one resource. The master
can simply do an IN on its channel end: it will block until
there is data ready for it.

Now the problem at hand. The V reg on every resource is
only the low 16 bits; the high 16 bits are provided by PS
reg 1 (see "processor status configuration" in the manuals).
At the start of your program you should do something like

Code: Select all

ldc r10,0x000c
get r11,ps[r10]
ldc r10,0x010c
set ps[r10],r11
and it should get further.
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segher
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Postby segher » Sat Dec 28, 2013 3:27 pm

segher wrote:

Code: Select all

ldc r10,0x000c
get r11,ps[r10]
ldc r10,0x010c
set ps[r10],r11
I think that should be 000b resp. 010b,
and the datasheet has a bug :-(
dwelch67
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Postby dwelch67 » Sun Dec 29, 2013 4:19 am

Thanks, trying to use events with one thread first then once that works add more threads...Appears to be the way XCC generated code is doing it.

Will try your suggestion, thank you.
David
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Postby dwelch67 » Sun Dec 29, 2013 4:24 am

0xc, 0x10c causes a trap.

0xb,0x10b, fixes the vector, but it still ends at the same place.

Code: Select all

stdcore[0]@0- -A-p-.----0001004a (t0inner             +  2) : setv    res[r5(0x2)], r11(0x1004e) @205
stdcore[0]@1- -p-A-.----.0001005e (t1inner             +  2) : bt      r2(0x9), -0x2 @207
stdcore[0]@0-P-A-p-.----0001004c (t0inner             +  4) : waiteu   @209
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x8), r2(0x9), 0x1 @211
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x8), -0x2 @215
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x7), r2(0x8), 0x1 @219
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x7), -0x2 @223
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x6), r2(0x7), 0x1 @227
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x6), -0x2 @231
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x5), r2(0x6), 0x1 @235
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x5), -0x2 @239
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x4), r2(0x5), 0x1 @243
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x4), -0x2 @247
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x3), r2(0x4), 0x1 @251
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x3), -0x2 @255
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x2), r2(0x3), 0x1 @259
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x2), -0x2 @263
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x1), r2(0x2), 0x1 @267
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x1), -0x2 @271
stdcore[0]@1- -weA-.----.0001005c (t1inner             +  0) : sub     r2(0x0), r2(0x1), 0x1 @275
stdcore[0]@1- -weA-.----.0001005e (t1inner             +  2) : bt      r2(0x0), -0x2 @279
stdcore[0]@1- -weA-.----.00010060 (t1inner             +  4) : out     res[r6(0x102)], r9(0x10) @283
stdcore[0]@0Event caused by res 0x00000002, V=0x0001004e, EV=0x00000002 @287

Code: Select all

_start:
    ldc r1, 10
notmain:                
    sub r1,r1,1
    bt r1, notmain

ldc r10,0x000b
get r11,ps[r10]
ldc r10,0x010b
set ps[r10],r11

    ldc  r11, 0x6       # the I/O ports need a clock
    setc res[r11], 0x8  # setci
    setc res[r11], 0xf  # setci

    # define XS1_PORT_32A 0x200000
    ldc r9,0x2000
    shl r9,r9,8
    setc res[r9],0x8    # turn the port on
    ldc r1,0x6          # give it a clock
    setclk res[r9],r1


    getr r5,2
    getr r6,2
    setd res[r5],r6
    setd res[r6],r5

    getr r4,0x3         # get a synchronizer

    getst r0,res[r4]    # allocate a thread
    ldap r11,thread1    # get address for the code for new thread
    init t[r0]:pc,r11   # set pc for new thread
    set t[r0]:r5,r5
    set t[r0]:r6,r6

    msync res[r4]       # start all allocated threads
    bu thread0          # give thread 0, the main thread, a place to go

thread0:
    ldc r0,0x0

    clre
    eeu res[r5]

t0outer:
    out res[r9],r0
t0inner:
    ldap r11,t0thread1
    setv res[r5],r11
    #setv res[r6],r11
    waiteu

t0thread1:
    in r10,res[r5]
    #outct res[r5],1
    xor r0,r0,r10
    bu t0outer

thread1:
    ldc r9,0x0010
    ldc r3,11
t1outer:
    mov r2,r3
t1inner:
    sub r2,r2,1
    bt r2,t1inner
    out res[r6],r9      # send some data to thread0
    #chkct res[r5],1
    bu t1outer
dwelch67
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Postby dwelch67 » Sun Dec 29, 2013 4:31 am

which manual? I searched the site for that string and got no hits.
dwelch67
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Postby dwelch67 » Sun Dec 29, 2013 4:40 am

I agree with you, should be 0xB.
Processor status registers
The following are processor status registers that are accessed using GETPS and
SETPS. The regsiter number must be translated to a resource ID by shifting the
register number left 8 bits, and oring 0x0B in (the resource ID that identifies a
processor control register).
...
0x00 PS_RAM_BASE
0x01 PS_VECTOR_BASE RW
read PS_RAM_BASE 0x00b, write ps vector base 0x10b...
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Postby dwelch67 » Sun Dec 29, 2013 4:47 am

Yet another tangent. The XS1-G System Specification and XS1-L System Specification have the Processor Status Registers defined, different set of registers of course between the G and L, although the ram base and vector base are in the same places. is there an XS1-U System Specification manual somewhere or in the works (this is really an XS1-U on the startKIT right?)

Thanks,
David
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segher
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Postby segher » Sun Dec 29, 2013 11:51 am

dwelch67 wrote:which manual?
The datasheet, the one I pointed you to.

You can use the L system specification; U and A series
packages contain L chips. G is older.
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segher
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Postby segher » Sun Dec 29, 2013 12:00 pm

I don't see what's wrong with your code or why the
simulator won't handle your event. You didn't post the
full log, maybe there is something obvious wrong earlier.

But again, there is nothing using events buys you here; just have
all threads block if there is nothing to do (e.g., the master
thread can just do an IN on its channel end; the master
thread will then pause until someone has sent it data).
dwelch67
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Postby dwelch67 » Mon Dec 30, 2013 12:23 am

Didnt want to fill up the forum with a log. You could easily sim it yourself if there is something missing...

I thought you said that multiple threads feeding one channel is a no-no. Please teach how to use a single IN to watch multiple communication paths (one to seven other cores/threads/tasks). As mentioned I am trying to get one to work then will replace that with many.

Thanks,
David

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