Aggregate Device delay issues on macOS

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
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Aggregate Device delay issues on macOS

Postby SGapp » Tue Oct 27, 2020 4:54 pm

Hey all,
I have designed a microphone array to USB interface that can process 16 MEMS microphones per interface. My system is based on the xCore200 Microphone Development Kit. In order to exceed the 16 microphone limit, I added a clock master/slave option that allows to cascade multiple interfaces. The clock master/slave refers to the audio clock. The system operates with a sample frequency of 48kHz. The clock master generates a 48kHz sync signal for the clock slave. The clock slave derives its audio master clock from that 48kHz signal. I used the CS2100 (Datasheet) to multiply the incoming 48kHz to 12.288MHz. It turned out that there is no phase relation between the CS2100 input and output, which adds a maximum sample error of one period of the 12.288MHz clock. The MEMS microphones use a 3.072MHz clock from which the audio data is decimated to the desired 48kHz sample rate.

I used two interfaces in master/slave mode to validate an array of 32 microphones and performed six measurements. Between each measurement both interfaces were disconnected and connected again from their power source. The measurement setup was as follows:
One interface as clock master, the other as clock slave. Both connected to a MacBook Pro, running macOS Catalina, via an USB C hub. I created an aggregate device which contains both interfaces with no drift correction active. A block diagram of the setup is attached below.
The 16 microphones that each interface can process are working fine. When measuring the delay between the two cascaded interfaces it became apparent that there is a non-deterministic delay. The delay ranged from 0 to 10 samples, with hitting 0 samples only once. I am looking for explanations for that behavior since I don't have a clue, why this is happening. My first guess would be the USB C hub has something to do with it but I am not sure.

Does anybody have experience with that issue and can share their experience on it?
Thanks in advance!
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Postby mon2 » Wed Oct 28, 2020 10:02 am

Hi. Not an audio developer so only observing from a 50 ft view here..

1) see the comments from infinite, especially the last paragraph


2) maybe a good idea to consider to daisy chain the XMOS CPU(s) over xlinks and lvds transceivers (to allow for signal integrity over a longer cable drive) for this interconnect. With such a setup, you will have more control to synchronize your sampling effort.

Just my suggestions.
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Joined: Mon May 04, 2020 4:32 pm
Location: Berlin, Germany

Postby SGapp » Thu Oct 29, 2020 12:42 pm

Hi mon2,
thanks for your fast response and your suggestions.
1) I basically implemented the suggestion from infinite's comment. I derice the audio MCLK from the 48kHz sync signal. Using 48kHz as a wordclock signal is the typical approach in pro audio applications. This guarantees sampling at the same time.

2) Daisy chaining seems to be a good back up idea. Will have a look into that.

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