USB Audio Reference Design 2.0 Performance.

[AudioBoy]

Hello colleagues.

I have some question to the developers about the USB Audio 2.0 design.

Now I run Thyscon EVAL driver.
I unsolder the codec chip and connect DAC_DATA and ADC_DATA together, so I make the Loop.

1) When I run it in a regular USB mode with ARTA or SpectraPlus software (both these program does not support ASIO), I saw that the sample rate is remain the same, 44.1kHz and it is not changed when I change it in the software.
This is EVAL driver feature or what?

2) When I run it with ASIO supported PC software, the sample rate is changed correctly.

3) When I send the "Digital Zero" signal, I do not see the real "Zero" at DAC_DATA wire

xmos_digital_zero.jpg

The "sort pulse" is always ~ at the center, the wide pulse - is ~ 1/2 of LRCK width (so it is 0xFFFF).

And, I do not see 24 bit signal even with errors.
The noise floor is ~ -140dBFS. For real 24bit zero signal it must be much lower.

2) When I send 1kHz sin wave, I got this picture:

xmos1khz.png

Notice a lot of spikes, surrounding the fundamental frequency, and the noise floor ~ -130dBFS.

What should be (the same PC software, another USB_I2S interface) with 16 and 24 bit:

sin1k_9616_24.png

It looks like XMOS work at 16 bit mode.

Is it possible to get the "Clear Signal" with XMOS USB Audio?
We want to replace the existing USB_I2S interface in our volume production device, and we check the various solutions. I was sure that XMOS is the best solution, by today's measurements really disappoint me.
------
P.S. What does it mean "one clock domain" in the driver's description?
(The driver, which can be obtained with PID&VID after purchasing of 150 chips)

[AlexAdvice]

Hello AudioBoy,

I think you have a PC adjustment problem.
I also used SpectraPlus (5.0.26 - w/o ASIO support), and the sample rate cannot be changed. Also in ARTA.
Even with the latest version (SpectraPlus-SC), where ASIO support is claimed - Spectra does not see Thesycon ASIO driver.

However, you can set the sample rate you need at the windows' audio properties.
All this - under Win7.
With WinXP is much better - sample frequency can be changed directly from the SpectraPlus/ARTA without the ASIO.



The harmonics problem that you have observed - maybe because the real sample rate and what the Spectra+ expect, are not the same.
I've run it without any problem in loop condition, the noise floor was ~-180dBFS with signal, and less then -200dBFS without ("Digital Zero").

Reg.

[AudioBoy]

Hi Alex, I'll try with WinXP.
Thanks.

[AlexAdvice]

Hi AudioBoy,

what driver do you use?
And what formware revision you have in you Ref.Design board?

I just check that my Ref.Design board works fine with 2.15.0 EVAL Thesycon Driver, but my custom board with 6.6.0 firmware - does not work with this driver.

I tried to install the driver, which I got with xmos board from e-bay - and both, Ref.Design and my own boards works perfect with this driver.
It is very unclear, because this driver has the same revision - 2.15.0!

Regards.

[Ross]

Everything is being re-sampled in the windows mixer - you can change the sample frequency/bit-depth in the Windows audio control panel. All of your plots seem to show rate-conversion occurring.

[AlexAdvice]

Hi Ross,

can you tell some words about the driver problem, I talked above?

Regards.

[Ross]

Hi Ross,

can you tell some words about the driver problem, I talked above?

Regards.

One clock domain means one "clock source unit" only - in your case this is a local clock source.

The restriction means that you cannot select another clock source such as one derived from an external S/PDIF input stream for example.

[AlexAdvice]

Hi Ross,
thanks.

Now I understatnd. PReviously, I'm afraid that it means that 2 clock frequencies are not possible (44x and 48x).

And anorher question about the clock - I want to put galvanic isolation to I2S port, and to avoid high MCLK jitter, MCLK oscillator will be at isolated part.
So, it is possible that sometimes isolated part is not powered, and MCLK will not reach XMOS CPU.
What will happened?

I ask, because I have seen some similaar designs, where clock multiplexer was implemented at the CPU side. There was one "main oscillator" at isolated part, it goes to CPU part.
CPU part also consists of oscillator. CPU receive MCLK from multiplexor, comtroled by the presence of the main clock.
If the main clock from the isolated part is availiable, it clocks the CPU, if it is not availiable- CPU clocked from th e secondary one.

I think this is an overkill, if nothing wil happens with CPU w/o MCLK signal. I mean - the CPU and PC driver will not hang, not necessary to disconnect/connect CPU to USB when MCLK appears.
Of course, there will be no data transmittion w/o MCLK.

[Ross]

Hi Ross,
thanks.

Now I understatnd. PReviously, I'm afraid that it means that 2 clock frequencies are not possible (44x and 48x).

nope, that certainly is possible!

And anorher question about the clock - I want to put galvanic isolation to I2S port, and to avoid high MCLK jitter, MCLK oscillator will be at isolated part.
So, it is possible that sometimes isolated part is not powered, and MCLK will not reach XMOS CPU.
What will happened?

I ask, because I have seen some similaar designs, where clock multiplexer was implemented at the CPU side. There was one "main oscillator" at isolated part, it goes to CPU part.
CPU part also consists of oscillator. CPU receive MCLK from multiplexor, comtroled by the presence of the main clock.
If the main clock from the isolated part is availiable, it clocks the CPU, if it is not availiable- CPU clocked from th e secondary one.

I think this is an overkill, if nothing wil happens with CPU w/o MCLK signal. I mean - the CPU and PC driver will not hang, not necessary to disconnect/connect CPU to USB when MCLK appears.
Of course, there will be no data transmittion w/o MCLK.

The reference software requires the XMOS device to have a MCLK input. This is used to clock I2S and also async feedback to the host. I would suggest that the MCLK input is never removed from the XMOS input unless the software is expecting it i.e. at a sample rate change.

[AlexAdvice]

Hi Ross,

of course, MCLK is need for operation, and nobody think that w/o power at isolated part the system will operate.
I asked something else - do we need to have backup internal MCLK at CPU side, if the main MCLK (at isolated side) is not powered on?
If the solution with 2 oscillators, multiplexer and mclk-detector is must?
Or in case of MCLK missing, the system will wait for isolated part to be powered on?