Principal Physical Design Engineer - XMOS

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Principal Physical Design Engineer - XMOS

Post by jason »

XMOS is seeking to expand this team with a multi-skilled, highly valued member of the physical design team with specialization in implementing ultra deep sub micron digitial chip designs.


BSc, MSc or above in Electronic Engineering or related degree (at least a 2:1 from a top tier university)


Min 5 years in Analogue, Mixed Signal or High Speed Digital Design in USM CMOS process nodes (90nm and below).

Essential Skills

* Strong understanding of analogue circuits and subsystems, e.g. IO, PLL, SRAM, Non-Volatile Memory, DAC, ADC, DC-DC
* Strong spice knowledge, preferably in HSPICE or ELDO
* Good scripting skills, preferably in Perl and TCL
* Experience of semi-custom or ASIC design tools, e.g. Synthesis, PNR, STA, DRC, LVS, Power And Droop Analysis
* Experience of integrating EDA tools
* Experience of clocking strategy design, low power design
* Knowledge of cell/macro timing and power characterization an advantage
* Knowledge of digital timing flows an advantage
* Knowledge of chip packaging an advantage
* Knowledge of GALS, asynchronous design techniques an advantage

Key Responsibilities

To be a key contributor towards a team producing high-speed processor designs, this could include:

* Evaluation of 3rd party analogue IP offerings
* Development of key design strategies, e.g. chip clocking, power gating, power grid design, on-chip decoupling strategies
* Design and characterization of cells to augment current libraries
* Analysis of chip design, e.g. power consumption, decoupling, timing
* Contribute to the physical design and analysis of the chips
* Evaluation of process nodes and development of design margins and guidelines
* Flow development

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