How to communicate with PTP linux PC? Topic is solved

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nick
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Re: How to communicate with PTP linux PC?

Postby nick » Tue Oct 20, 2020 2:20 pm

Hi,
back here because I tried to connect two XMOS EVM boards: a multichannel and an explorer with an external oscillator (CS2000). I want to verify the quality of the ptp_output_test_clock() as clock recovery method.

I verified that the two boards have different MAC addresses and I reduced PTP_DEFAULT_GM_CAPABLE_PRIORITY1 of one board in order to make it the PTP master. On this board the oscillator is free running.
On the other board, the PTP slave, it runs the ptp_output_test_clock() task that should do the clock recovery (I'm feeding this clock to the hardware PLL I have on board). The output frequency I used is 960 Hz, same as for AVB.
On both boards I'm also running the ptp_server() task.

I enabled the macro DEBUG_PRINT_AS_CAPABLE to see the value pdelay.

1) I noticed that both the PTP master and the PTP slave calculate the pdelay. And I think this is ok, because in the 802.1as both the devices ask for pdelay request. But I was wondering why this two values are different. I expected them to be equal since it's a direct link. Am I wrong?

2) On console I see the PTP is locked. But with an oscilloscope I checked the TDM LRCLK at 48000 kHz on both boards and noticed that the signals were drifting. This doesn't happen with AVB firmware when one board is synchronized with the input stream. Anyway, even if ptp_output_test_clock() is not perfect, I expected to see at least an attempt of synchronization. Has anyone ever tried a similar setup?
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akp
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Postby akp » Tue Oct 20, 2020 9:28 pm

1. Are you confident the PHY delay is correct on both boards?

2. I didn't try exactly what you did, I did try to output a clock on two boards synchronized to a common master, and the output was synchronized if I remember correctly. But the phase error between the two was random, e.g. if one came into the network later than the other it would have a different phase offset.
nick
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Postby nick » Wed Oct 21, 2020 3:19 pm

1) With PHY delay do you mean the PTP path delay? In the previous post with "I think this is ok" I was referring to the fact that I think it's possible that each device calculate a different path delay (it wasn't clear in the post, my fault). However, in my setup I expected two identical path delay, because the firmware is the same and there's a direct connections between the 2 boards. If I'm not wrong the path delay is the delay introduced by ETH interface (ingress and egress time) + wire.

2) I can accept a phase error at this time. Maybe in the future I'll try to do something similar to the phase synchronization in AVB. Were you using the AVB firmware? Because with that it's ok. What device where you usign as PTP master?
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akp
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Postby akp » Wed Oct 21, 2020 3:24 pm

1. I meant the ingress and egress PHY delay settings for the PHY on each board.

2. I was using the AVB firmware but I was not using the input stream derived clock. I don't have any input streams. I was using local clock and simply running the pll reference from the ptp_output_test_clock() function. I have a linux PC running gPTP that the system synchronizes to.
nick
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Postby nick » Wed Oct 21, 2020 3:27 pm

1) Yes, they are identical. I'm compiling the same project for both boards (just changing pinout) and I didn't change them from the default value.

2) Interesting. I'll try your setup and let you know

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