Seminar:Modelling a SoC bus interconnect using an XMOS XMP64

[nassim]

University of Bristol

Reading group: Modelling a SoC bus interconnect using an XMOS XMP-64 board
27 Sep 2011 at 13:00 in MVB 3.36

Speaker: James Pallister

Abstract: A SoC modelling framework has been built for the XMOS XMP-64 board to simulate a shared memory system with multiple IP-cores injecting different distributions of traffic into a bus interconnect. The simulator keeps track of individual transactions going through the system, allowing the latency of each component to be examined. I will discuss the design of the simulator and some of the results we have obtained.

https://www.cs.bris.ac.uk/Research/Micr ... 9867200000

[phalt]

Oh interesting, I'm surprised I didn't pick up on this sooner. I might attend if I have some spare time, thanks for sharing!