I2S Ports synchronized by same clock in two parallel tasks

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MarcAntigny
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I2S Ports synchronized by same clock in two parallel tasks

Postby MarcAntigny » Fri Mar 26, 2021 4:29 pm

Hi,
We are developing using XU232-1024 chip for usb audio device. We aim at handling 16 outputs over I2S.
To do so, we use the reference design 6.15.2 with a modification in the audio/i2s part :
Instead of having one deliver task to handle 8 I2S IO, we have two deliver tasks running in parallel (that we call deliver1 and deliver2) that would handle each 8 I2S IO (to get the 16 I2S IO in total).
deliver1 task is managing the LRCLK and synchronizes with deliver2 when needed (at LRCLK change and to handle command from mixer).

The problem we have is that the I2S frame of deliver2 is one bitclock cycle behind the I2S frame of deliver1.
Image
Yellow : LRCLK / Blue : Bitclock
The dotted vertical cursor corresponds to when the I2S frame from deliver1 starts.
The plain vertical cursor corresponds to when the I2S frame from deliver2 starts.
(my scope is only two channels so I couldn't display everything at the same time)

All I2S port are clocked with the same bitclock clock block, so both frames should be starting at the same time.
Do you have any idea of what is happening ? Could the synchronization of the port on the bitclock be broken because we are using two tasks ?

Cheers,
Marc
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aclassifier
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Joined: Wed Apr 25, 2012 8:52 pm

Postby aclassifier » Tue Apr 27, 2021 8:12 pm

Sorry for not being able to help! But I have two somewhat related asides:

I am struggling with finding the (?) audio output driver for the 3.5 mm jack on the XK-USB-MIC-UF216 MIC_ARRAY board. Q1, any idea?..

So I stumbled upon your "we use the reference design 6.15.2". Q2: which one is this?

Update 1: Is this the one I'm looking for? AN00219: Low Resolution Delay and Sum Example as suggested in Microphone array AN00219 no sound

Update 2: I also know about this, but there is not so much "free code" there: (6.16.1alpha1).pdf]USB Audio Design Guide 110 pages!
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Øyvind Teig
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