Either I have miss configured the interface or miss understood how the configure_in_port_strobed_master function works. Can anyone help?
Data is added to the FIFO in bursts of 4 16 bit words (this happens at high speed so that by the time the XMOS processor has responded to the first word all four 16 bit words have been written).
Once there is data in the FIFO the p_fifo_data_ready line is driven high by the FIFO and this which is trapped by the select case.
The p_debug line is toggled as each of the 4 words are transferred into the processor.
As the p_data_bus is configured using configure_in_port_strobed_master, the p_rd_req line is driven by the XMOS and I would expect that data would be read into the XMOS on the next rising clock edge, BUT looking at the attached scope trace the p_debug line shows that the XMOS is reading data in at incorrect and inconsistent times. I have added blue vertical lines where I would expect the XMOS to read the data and would expect the yellow trace to toggle just after the blue lines, but that is not what happens.
Code: Select all
on tile[0] : port p_debug = XS1_PORT_1O;
in port p_fifo_data_ready = on tile[0]:XS1_PORT_1F; // goes high to indicate there is data in the FIFO
in buffered port:16 p_data_bus = on tile[0]:XS1_PORT_16A; // 16bit data bus from FIFO
out port p_rd_req = on tile[0]:XS1_PORT_1N; // drive port high to read data from FIFO
on tile[0] : out port p_rd_clk = XS1_PORT_1E;
on tile[0] : clock rd_clk = XS1_CLKBLK_4;
main ()
{
unsigned short temp_data_input[256];
timer tmr;
unsigned t, timeout;
configure_clock_rate (rd_clk , 100, 10); // 100/10 = 10 MHz
configure_port_clock_output(p_rd_clk, rd_clk );
configure_in_port(p_fifo_data_ready, rd_clk); // read fifo_data_ready on clk edge
configure_in_port_strobed_master(p_data_bus, p_rd_req, rd_clk); // Drive rd_req high to read data
start_clock (rd_clk);
clearbuf(p_data_bus);
p_debug <: 0;
while(TRUE)
{
select
{
case p_fifo_data_ready when pinsneq(0) :> f: // wait for ready data when data is ready
p_debug <: 1;
p_data_bus :> temp_data_input[0]; // read 16 bit data
p_debug <: 0;
p_data_bus :> temp_data_input[1]; // read 16 bit data
p_debug <: 1;
p_data_bus :> temp_data_input[2]; // read 16 bit data
p_debug <: 0;
p_data_bus :> temp_data_input[3] ; // read 16 bit data
p_debug <: 1;
tmr :> t;
timeout = t + 20; // timeout in 200ns
p_debug <: 0;
break;
}
}
}
The scope trace below shows the following signals:
Ch1 p_debug
ChA p_rd_clk
ChB p_fifo_data_ready
Ch2 p_rd_req