LRCK no output under 45M/49M MCLK

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
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akp
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Post by akp »

I won't say it's impossible to solve it in software. It is very difficult, though. I think you might have a solution if you need to keep your 24 MHz MCLK. You will have to run the XMOS IP as I2S slave rather than I2S master. And set up the TLV320DAC3120 PLL to generate BCLK at 64 * 48 kHz = 3.072 MHz and WCLK at 48 kHz.


twittich
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Post by twittich »

Solved it by changing the routing and calculation of the clocks and works now...
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akp
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Post by akp »

Great. Running with 24.576 now?
twittich
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Post by twittich »

Yes i'm getting now the 24.576 MHz, generated by the codec and back to the xmos. Now all clocks and samples rates are correct.
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GeorgeIoak
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Post by GeorgeIoak »

akp wrote: Tue Nov 26, 2019 6:34 pm What IP are you referring to? If it's the USB reference design I don't know if it's possible. It's possible with lib_i2s with the i2s frame based master.
Would you mind providing some details on how I switch to using lib_i2s