LRCK no output under 45M/49M MCLK
I won't say it's impossible to solve it in software. It is very difficult, though. I think you might have a solution if you need to keep your 24 MHz MCLK. You will have to run the XMOS IP as I2S slave rather than I2S master. And set up the TLV320DAC3120 PLL to generate BCLK at 64 * 48 kHz = 3.072 MHz and WCLK at 48 kHz.
Solved it by changing the routing and calculation of the clocks and works now...
Great. Running with 24.576 now?
Yes i'm getting now the 24.576 MHz, generated by the codec and back to the xmos. Now all clocks and samples rates are correct.
- GeorgeIoak
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