Finally solved the XS1 External SRAM problem

Off topic discussions that do not fit into any of the above can go here. Please keep it clean and respectful.
User avatar
XCore Legend
Posts: 1274
Joined: Thu Dec 10, 2009 10:20 pm

Finally solved the XS1 External SRAM problem

Post by Folknology »

April Fools post, please ignore..

After 12 months of trying I have finally solved how to increase the amount of memory mapped SRAM on an XS1. The only limitation is that it is L2 package specific:

When Xmos packaged the L2 they actually used 2 full XS1 dies inside the packaging, in order to do this they had to do some clever juggling with the multiplexing of IO pins and the internal connections for the inter die links. The dies themselves actually have a lot more connections than are exposed by the regular packaging. Whilst experimenting with the various port and link settings on my L2 board I noticed something very strange. On my proto l2 board the oscillator and debug pins had an accidental solder bridge which when booted up seemed to place the L2 in a strange mode where the ports on core 0 didn't seem to operate according to my C test thread. After applying my logic probe I noticed that the bit patterns on port 16A seemed to be counting in binary and then suddenly jumping to a new state and counting up again. So I checked the code to see if I was doing something wrong and during the debug I noticed I had a runaway pointer. I then fixed the code and checked again, still the port wasn't doing as it should, but the binary counting had ceased.

Any how to cut a long story short it turns out the all of the IO pins on core 0 were inoperable, because they had some how been multiplexed to part of the internal XS1 core 0 address bus, well at least port 16A was, it appeared to be multiplexed to some upper part of the internal address bus. That is why the run away pointer was causing the binary counting pattern on those ports. I then investigated further and found that port 16B was carrying multiplexed data bus from the internal XS1 using a double word transfer, holy crap! I suddenly realised that this is operating as an undocumented external SRAM interface OMG!

Now clearly this mode of operating isn't supported by Xmos officially and it also means that you can't use one of the cores for IO, but you can extend the SRAM memory address space significantly using this undocumented hack. I am in the process of working out the function of the remaining 1 bit ports which I believe to be multiplexed as memory timing and page signals etc..and I'll get those details out tomorrow, but In the meantime I couldn't wait to let everyone know the news today because this represents an amazing hack which might allow us to finally run Linux on an L2!

Last edited by Folknology on Sat Apr 02, 2011 8:48 pm, edited 1 time in total.

User avatar
New User
Posts: 2
Joined: Thu Mar 17, 2011 8:38 pm

Post by TheBeaver »

User avatar
Respected Member
Posts: 363
Joined: Thu Dec 10, 2009 10:17 pm

Post by Berni »

Ah now you probably ruined there plans on secretly unveiling the external memory bus. :lol:
User avatar
XCore Addict
Posts: 234
Joined: Thu Dec 10, 2009 11:11 pm
Location: Newcastle, UK

Post by TonyD »

Nice find :)