xCONNECT and xTAG between two xC-200 processors
Posted: Wed Feb 16, 2022 9:34 pm
I am working on a design project that in one version will use an XL232-1024-FB374, and in another adds an XE216-512-FB236 to provide an Ethernet interface. I’m starting with the assumption that as the XL232 is common to both designs, in the case of the dual processor version that it will be the primary processor and the XL216 the secondary one. The external flash memory is connected via the QSPI interface on the XL232 in both instances, with the anticipation for software updates via the XL216 Ethernet interface on the two processor version. I understand using the left-hand column priority principle, that any I/O pins used for xCONNECT interfaces are stripped out of the respective multi-bit ports. So in the instance of a full xTAG connector implementation 8D4-8D7 and8 16B12-16B15 are not available in on their respective ports, but the other bits (8D0-8D3 and 16B00-16B11) are available. Is this correct please? I have X0D40-X0D43 spare on both processors. X0D40 XL0 In 1 XL1_DN1 8D4 16B12 X0D41 XL0 In 0 XL1_DN0 8D5 16B13 X0D42 XL0 Out 0 XL1_UP0 8D6 16B14 X0D43 XL0 Out 1 XL1_UP1 8D7 16B15 How should the daisy-chained JTAG connections be made from the 20-way header to the two processors please? I understand that the TDI input pin 5 on the 20-way header goes to the primary processor, its TDO output goes to the TDI input of the secondary processor, and its TDO output goes back to the TDO pin 13 on the 20-way header, likewise TMS and TCK go to both processors, so it’s the other pins I’m enquiring about (the four xCONNECT connections plus DEBUG_N and RST_N). 1 NC (+5V) 2 NC 3 NC (MSEL) 4 GND 5 TDI 6 XL1_UP1 7 TMS 8 GND 9 TCK 10 XL1_UP0 11 DEBUG_N 12 GND 13 TDO 14 XL1_DN0 15 RST_N 16 GND 17 NC (UART_RX) 18 XL1_DN1 19 NC (UART_TX) 20 GND For the interconnections between the two processors, I have some options for connecting them, again using the left-hand column priority principle I have the following 2-wire and 5-wire interfaces available on the XL232: X1D64 XL2 In 1 32A13 X1D65 XL2 In 0 32A14 X1D66 XL2 Out 0 32A15 X1D67 XL2 Out 1 32A16 X2D61 XL6 In 4 32A10 X2D62 XL6 In 3 32A11 X2D63 XL6 In 2 32A12 X2D64 XL6 In 1 32A13 X2D65 XL6 In 0 32A14 X2D66 XL6 Out 0 32A15 X2D67 XL6 Out 1 32A16 X2D68 XL6 Out 2 32A17 X2D69 XL6 Out 3 32A18 X2D70 XL6 Out 4 32A19 The XL216 has the following 2-wire and 5-wire interfaces available: X0D49 XL5 In 4 32A00 X0D50 XL5 In 3 32A01 X0D51 XL5 In 2 32A02 X0D52 XL5 In 1 32A03 X0D53 XL5 In 0 32A04 X0D54 XL5 Out 0 32A05 X0D55 XL5 Out 1 32A06 X0D56 XL5 Out 2 32A07 X0D57 XL5 Out 3 32A08 X0D58 XL5 Out 4 32A09 X0D61 XL6 In 4 32A10 X0D62 XL6 In 3 32A11 X0D63 XL6 In 2 32A12 X0D64 XL6 In 1 32A13 X0D65 XL6 In 0 32A14 X0D66 XL6 Out 0 32A15 X0D67 XL6 Out 1 32A16 X0D68 XL6 Out 2 32A17 X0D69 XL6 Out 3 32A18 X0D70 XL6 Out 4 32A19 I assume that there is no particular advantage in choosing one set of ports over another? What is the available functionality and also any limitations for the use of 2-wire and 5-wire xCONNECT interfaces please? The xCONNECT Architecture is quite a few years old now and whilst gives information about maximum speed, there isn’t much that’s specifically relevant to xC-200 processors, likewise the available application notes. Also, I’ve been advised to restrict critical timing chanends/interfaces to within a pair of tiles (Tile 0 & 1 or Tile 2 & 3) and not to make such connections between pairs of tiles, is this established good practice please?