Re: How to communicate with PTP linux PC?
Posted: Tue Oct 20, 2020 2:20 pm
Hi,
back here because I tried to connect two XMOS EVM boards: a multichannel and an explorer with an external oscillator (CS2000). I want to verify the quality of the ptp_output_test_clock() as clock recovery method.
I verified that the two boards have different MAC addresses and I reduced PTP_DEFAULT_GM_CAPABLE_PRIORITY1 of one board in order to make it the PTP master. On this board the oscillator is free running.
On the other board, the PTP slave, it runs the ptp_output_test_clock() task that should do the clock recovery (I'm feeding this clock to the hardware PLL I have on board). The output frequency I used is 960 Hz, same as for AVB.
On both boards I'm also running the ptp_server() task.
I enabled the macro DEBUG_PRINT_AS_CAPABLE to see the value pdelay.
1) I noticed that both the PTP master and the PTP slave calculate the pdelay. And I think this is ok, because in the 802.1as both the devices ask for pdelay request. But I was wondering why this two values are different. I expected them to be equal since it's a direct link. Am I wrong?
2) On console I see the PTP is locked. But with an oscilloscope I checked the TDM LRCLK at 48000 kHz on both boards and noticed that the signals were drifting. This doesn't happen with AVB firmware when one board is synchronized with the input stream. Anyway, even if ptp_output_test_clock() is not perfect, I expected to see at least an attempt of synchronization. Has anyone ever tried a similar setup?
back here because I tried to connect two XMOS EVM boards: a multichannel and an explorer with an external oscillator (CS2000). I want to verify the quality of the ptp_output_test_clock() as clock recovery method.
I verified that the two boards have different MAC addresses and I reduced PTP_DEFAULT_GM_CAPABLE_PRIORITY1 of one board in order to make it the PTP master. On this board the oscillator is free running.
On the other board, the PTP slave, it runs the ptp_output_test_clock() task that should do the clock recovery (I'm feeding this clock to the hardware PLL I have on board). The output frequency I used is 960 Hz, same as for AVB.
On both boards I'm also running the ptp_server() task.
I enabled the macro DEBUG_PRINT_AS_CAPABLE to see the value pdelay.
1) I noticed that both the PTP master and the PTP slave calculate the pdelay. And I think this is ok, because in the 802.1as both the devices ask for pdelay request. But I was wondering why this two values are different. I expected them to be equal since it's a direct link. Am I wrong?
2) On console I see the PTP is locked. But with an oscilloscope I checked the TDM LRCLK at 48000 kHz on both boards and noticed that the signals were drifting. This doesn't happen with AVB firmware when one board is synchronized with the input stream. Anyway, even if ptp_output_test_clock() is not perfect, I expected to see at least an attempt of synchronization. Has anyone ever tried a similar setup?