Xmos xu208 12 channel input Topic is solved

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Ezreal
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Xmos xu208 12 channel input

Postby Ezreal » Thu Oct 24, 2019 5:22 pm

hi!
I am using usb_audio_6.15.2 with xu208-128-qf45.With 8 channel input it works well on 1 TDM data line!But in my appalication it has 12 input,what should i do to make it working?Is it possible that has 12 channels input with 1 TDM data line?
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akp
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Postby akp » Thu Oct 24, 2019 7:28 pm

I would say 12 ch TDM is non-standard. I don't know if you would have an ADC or DAC that would work with that, unless you have some other kind of custom solution. Best would be 16 ch TDM I think, with 4 unused channels. Other options would be two TDM 8 ch data lines, where 4 of those channels are unused. Or you could have 3 TDM 4 ch data lines...

good luck
fabriceo
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Postby fabriceo » Thu Oct 24, 2019 8:17 pm

about the xu208 and the small amount of 1bit port available
would it be realistic to use a 4 bits ports upto 192k and then the unzip function 3 time to recover quad bits I2S into 4 registers ? The app note about zip unzip is touching that idea.
https://www.xmos.com/download/AN10129:- ... .2rc1).pdf
of course a lot has to be rewritten in the Deliver function of audio.xc but that worth a try :)
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akp
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Postby akp » Thu Oct 24, 2019 9:16 pm

I am not sure what sample rate the OP requires. I am pretty sure from when I tested it, the zip/unzip won't work with a 24.576 MHz BCLK. Therefore, it will be impossible to get TDM128 (i.e. 4ch @ 32 bit/ch) at 192 kHz as that would require a 128 * 192 kHz = 24.576 MHz.

On the other hand, it will work with a 12.288 MHz BCLK. So you should be able to do 4 ch @ 96 kHz to get 16 TDM channels (4 unused) on a 4 bit port. Or you could probably get 192 kHz @ 16 bit/sample if that's acceptable. An alternative would be to possibly use two 4 bit ports but you'd want to run them in separate cores I guess, which the OP probably doesn't have. There aren't a lot of spare cycles using the zip/unzip functionality so like you say the audio.xc rewrite will be fun. I would aim for maybe 48 kHz first but what do I know.
Ezreal
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Postby Ezreal » Fri Oct 25, 2019 3:24 pm

thanks for reply!
now i use 2 TDM data line each for 8 channels input with 8*32*48KHz = 12.288MHz,it can solve my issues perfectly!

unfortunately i met a new problem,my code stop in */module_usb_audio/audio.xc:339 p_lrclk <: 0 @ tmp when debuging.
i am stuck! does anyone meet this?

the following is CDT Build Console,it seems no error

Creating app_usb_aud_custom_XU208_HW.xe
Constraint check for tile[0]:
Cores available: 8, used: 6 . OKAY
Timers available: 10, used: 8 . OKAY
Chanends available: 32, used: 17 . OKAY
Memory available: 131072, used: 57880 . OKAY
(Stack: 3732, Code: 40056, Data: 14092)
Constraints checks PASSED.
xmap: Warning: port "XS1_PORT_1F" on tile[0] is not connected to any pins in this package.
xmap: Warning: port "XS1_PORT_1G" on tile[0] is not connected to any pins in this package.
xmap: Warning: port "XS1_PORT_1E" on tile[0] is not connected to any pins in this package.
xmap: Warning: port "XS1_PORT_1H" on tile[0] is not connected to any pins in this package.
xmap: Warning: port "XS1_PORT_1J" on tile[0] is not connected to any pins in this package.
xmap: Warning: port "XS1_PORT_1K" on tile[0] is not connected to any pins in this package.
xmap: Warning: port "XS1_PORT_1I" on tile[0] is not connected to any pins in this package.
Build Complete

22:21:10 Build Finished (took 1m:35s.858ms)
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akp
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Postby akp » Fri Oct 25, 2019 3:53 pm

Not really familiar with this IP on the XU208. Sorry. Assuming you did clean and build? Are you getting an exception?
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mon2
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Postby mon2 » Fri Oct 25, 2019 7:12 pm

Some relevant dialog here on your IP issue:

viewtopic.php?f=37&t=5760
Ezreal
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Postby Ezreal » Sat Oct 26, 2019 11:04 am

mon2 wrote:
Fri Oct 25, 2019 7:12 pm
Some relevant dialog here on your IP issue:

viewtopic.php?f=37&t=5760
thans for your reply!

In viewtopic.php?f=37&t=5760,it said there may have two reasons for the issue.
1)MCLK is not present-----I measure MCLK with oscilloscope.MCLK = 24.576MHz.but i am not sure if it can show MCLK is present.
2)You have set the CODEC_MASTER define which means the XMOS chip is expecting the DAC to provide the BCLK and LRCLK------I am particularly sure i haven't define CODEC_MASTER
but it still stuck in p_lrclk <: 0 @ tmp;
Ezreal
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Postby Ezreal » Sat Oct 26, 2019 11:24 am

i wrote a TDM demo to test,it can work well! the codes is like follows:

on tile[0]: port p_i2c = XS1_PORT_4C;
on tile[0]: port p_gpio = XS1_PORT_4E;

/* Ports and clocks used by the application */
on tile[0]: out buffered port:32 p_dout[1] = on tile[0]: {XS1_PORT_1P};
on tile[0]: in buffered port:32 p_din[1] = on tile[0]: {XS1_PORT_1N};
on tile[0]: in port p_tdm_mclk = on tile[0]: XS1_PORT_1A;
on tile[0]: out buffered port:32 p_tdm_bclk = on tile[0]: XS1_PORT_1M;
on tile[0]: out buffered port:32 p_tdm_fsync = on tile[0]: XS1_PORT_1O;
on tile[0]: clock clk_tdm_mclk = on tile[0]: XS1_CLKBLK_1;
on tile[0]: clock clk_tdm_bclk = on tile[0]: XS1_CLKBLK_2;

void es7210_i2c_init(client i2c_master_if i2c)
{
........
}

void i2s_handler(server i2s_callback_if tdm,
streaming chanend c_dsp)
{
printf("ldx i2s_handler\n");
int32_t in_samps[8] = {0};
int count = 0;
int32_t temp[10000];

while (1) {
select {
case tdm.init(i2s_config_t &?i2s_config, tdm_config_t &?tdm_config):
/* Configure the I2S bus */
tdm_config.offset = 1;
tdm_config.sync_len = 1;
tdm_config.channels_per_frame = 8;
break;

case tdm.restart_check() -> i2s_restart_t restart:
restart = I2S_NO_RESTART;
break;

case tdm.receive(size_t index, int32_t sample):
in_samps[index] = sample;
break;

case tdm.send(size_t index) -> int32_t sample:
sample = in_samps[index];
break; // end of select
}
}
};

static char gpio_pin_map[1] = {0};

int main() {
interface i2c_master_if i_i2c[1];
interface i2s_callback_if i_tdm;
interface output_gpio_if i_gpio[2];
streaming chan c_aud_dsp;


par {
on tile[0]: output_gpio(i_gpio, 1, p_gpio, gpio_pin_map);
on tile[0]: i_gpio[0].output(1);
on tile[0]: i2c_master_single_port(i_i2c, 1, p_i2c, 100, 0, 1, 0);
on tile[0]: es7210_i2c_init(i_i2c[0]);

on tile[0]: {
configure_clock_src_divide(clk_tdm_bclk, p_tdm_mclk, 1);
configure_port_clock_output(p_tdm_bclk, clk_tdm_bclk);
start_clock(clk_tdm_bclk);
tdm_master(i_tdm, p_tdm_fsync, p_dout, 1, p_din, 1,
clk_tdm_bclk);
printf("i2s i2s_master\n");
}
/* The application - loopback the I2S samples*/

on tile[0]: i2s_handler(i_tdm, c_aud_dsp);

}
return 0;
}

then i dig in the module_usb_audio's source code.in audioports.xc line 89,96,104,it has extra function,"configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);".
if i remove the functions,it would not stick in p_lrclk <: 0 @ tmp.but i still can't get BCLK.
dose anyone meet my issues?i can't find what i miss leading to this situation.
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mon2
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Postby mon2 » Sat Oct 26, 2019 10:24 pm

Hi.

printf is blocking and can kill your time sensitive IP.

Can you mask out these printf calls in your code and test again? Does that improve your results?

reference:
https://www.xmos.com/file/debug-printf-real-time/
* later you can review the above documentation to use printf in real-time if necessary

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