Xrun: Cannot load image, XCore 0 is not enabled
Posted: Fri Apr 05, 2019 10:47 pm
Hello All,
I'm working on a set of demo boards for some TI Audio DACs using the XEF216-512-TQ128, and I have just received my first order of prototype boards. Of the 10 I ordered, 4 of them are returning this error when I attempt to program them via JTAG. I've been following the recommendations from this support post to try and locate the cause, but so far nothing has worked.
1. The JTAG interface to the XCore has been disabled in the OTP security register. Not likely, devices should have been received in default configuration
2. The device is being permanently held in reset by the RST_N signal. Checked the RST_N signal, it is correctly releasing
3. No clock is being supplied to the device; or the clock frequency supplied to the device is unsuitable for the selected PLL multiplier. The PLL multiplier is set using the MODE pins and should be configured so that the XCore boots up at or below its maximum frequency. Further details on the MODE pins can be found in the relevant device datasheet. Supplied clock is at 24MHz, within datasheet recommendations. I've compared it to some other XMOS boards we have and it seems to be as clean or cleaner than those signals.
4. The VDD Core supply is outside of tolerance (see the device datasheet). Checked at source, pins, and at all bypass caps. Well within 10%.
5. The VDD PLL supply is outside of tolerance (see the device datasheet) or not present, or has a filter with too high a resistor. This will mean that the PLL is not locked and hence the XCore will be kept in reset. Checked this as well, filter is the recommended 4.75Ohm with 0.1uF cap, and voltage is within limit.
6. The power supplies have not been correctly sequenced. The VDDIO (and OTP_VDDIO if present) supply must be within specification (3.0V-3.6V) before the VDD Core supply is turned on; see the datasheet for details. This was my initial suspect. So I changed two of the caps to better follow the sequencing in the datasheet. After changing C102 (delays 3.3V rail) and C141 (delays RST_N signal) to 0.1uF, the 1V rail rises first, followed by the 3.3V rail slightly more than 10mS later. The RST_N signal is released about 400ms after that.
7. The device, especially the ground paddle, has not been correctly soldered to the board. This can either be in the form of not connected solder joints or shorted solder joints to other pins, ground or power. This is the last thing I'm checking, I have checked all of the pins around the device under a microscope and them seem to be okay. I can also see that some solder has flowed through the vias underneath the XMOS to the underside of the board, so I know that it was at least applied. However I am having one of the bad boards reflowed just to be sure.
I've included a capture of my power-up sequence and my schematic. If you have any other suggestions as to what it may be I'd appreciative. I'm running out of ideas on what else to look at.
I'm working on a set of demo boards for some TI Audio DACs using the XEF216-512-TQ128, and I have just received my first order of prototype boards. Of the 10 I ordered, 4 of them are returning this error when I attempt to program them via JTAG. I've been following the recommendations from this support post to try and locate the cause, but so far nothing has worked.
1. The JTAG interface to the XCore has been disabled in the OTP security register. Not likely, devices should have been received in default configuration
2. The device is being permanently held in reset by the RST_N signal. Checked the RST_N signal, it is correctly releasing
3. No clock is being supplied to the device; or the clock frequency supplied to the device is unsuitable for the selected PLL multiplier. The PLL multiplier is set using the MODE pins and should be configured so that the XCore boots up at or below its maximum frequency. Further details on the MODE pins can be found in the relevant device datasheet. Supplied clock is at 24MHz, within datasheet recommendations. I've compared it to some other XMOS boards we have and it seems to be as clean or cleaner than those signals.
4. The VDD Core supply is outside of tolerance (see the device datasheet). Checked at source, pins, and at all bypass caps. Well within 10%.
5. The VDD PLL supply is outside of tolerance (see the device datasheet) or not present, or has a filter with too high a resistor. This will mean that the PLL is not locked and hence the XCore will be kept in reset. Checked this as well, filter is the recommended 4.75Ohm with 0.1uF cap, and voltage is within limit.
6. The power supplies have not been correctly sequenced. The VDDIO (and OTP_VDDIO if present) supply must be within specification (3.0V-3.6V) before the VDD Core supply is turned on; see the datasheet for details. This was my initial suspect. So I changed two of the caps to better follow the sequencing in the datasheet. After changing C102 (delays 3.3V rail) and C141 (delays RST_N signal) to 0.1uF, the 1V rail rises first, followed by the 3.3V rail slightly more than 10mS later. The RST_N signal is released about 400ms after that.
7. The device, especially the ground paddle, has not been correctly soldered to the board. This can either be in the form of not connected solder joints or shorted solder joints to other pins, ground or power. This is the last thing I'm checking, I have checked all of the pins around the device under a microscope and them seem to be okay. I can also see that some solder has flowed through the vias underneath the XMOS to the underside of the board, so I know that it was at least applied. However I am having one of the bad boards reflowed just to be sure.
I've included a capture of my power-up sequence and my schematic. If you have any other suggestions as to what it may be I'd appreciative. I'm running out of ideas on what else to look at.