About xCORE200 extending the reference design to higher sample rates
Posted: Mon Dec 25, 2017 2:58 pm
I was a XMOS user form china.I have a few problems about the software reference design,my hardware platforms: XU208-128-c10,software: sw_usb_audio-[sw]_6.15.2rc1.
It can good warking at MCLK@512Fs,rates up to 384K/32Bit DOP 128, but when i change to 1024Fs (45.1548M and 49.152M) ,the clock generator was error,BCLK frequency started Instable,cause the LRCK error too. when playback 192KHz signal,the LRCK frequency was 170KHz,as rates higher the clock generator error is more obvious.
In softeare i changed some plases:
------------------------------------
/* Master clock defines (in Hz) */
#define MCLK_441 (1024*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (1024*48000) /* 48, 96 etc */
/* Maximum frequency device runs at */
#ifndef MAX_FREQ
#define MAX_FREQ (768000)
#endif
----------------------------------------
#ifndef CODEC_MASTER
static inline void doI2SClocks(unsigned divide)
{
switch (divide)
{
#if (MAX_DIVIDE > 32)
#error MCLK/BCLK Ratio not supported!!
#endif
#if (MAX_DIVIDE > 16) //For 1/16 mclks
case 32:
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
break;
#endif
-----------------------------------------------------------------------
There is something i missing to changed,i think. And the FAE of china can't give any help also there is no application note support.
So could anyone please tell me what's wrong with the software? Should i have to change which place ?
It can good warking at MCLK@512Fs,rates up to 384K/32Bit DOP 128, but when i change to 1024Fs (45.1548M and 49.152M) ,the clock generator was error,BCLK frequency started Instable,cause the LRCK error too. when playback 192KHz signal,the LRCK frequency was 170KHz,as rates higher the clock generator error is more obvious.
In softeare i changed some plases:
------------------------------------
/* Master clock defines (in Hz) */
#define MCLK_441 (1024*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (1024*48000) /* 48, 96 etc */
/* Maximum frequency device runs at */
#ifndef MAX_FREQ
#define MAX_FREQ (768000)
#endif
----------------------------------------
#ifndef CODEC_MASTER
static inline void doI2SClocks(unsigned divide)
{
switch (divide)
{
#if (MAX_DIVIDE > 32)
#error MCLK/BCLK Ratio not supported!!
#endif
#if (MAX_DIVIDE > 16) //For 1/16 mclks
case 32:
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
p_bclk <: 0xffff0000;
break;
#endif
-----------------------------------------------------------------------
There is something i missing to changed,i think. And the FAE of china can't give any help also there is no application note support.
So could anyone please tell me what's wrong with the software? Should i have to change which place ?