xCORE-AUDIO-HiRes-2 clock settings
Posted: Mon Jan 02, 2017 9:57 am
Hi,
I can not get my head around clocks generation and routing on xCORE-AUDIO-HiRes-2 platform.
1/ XHRA-2HPA datasheet is sketchy on details but fairly logical - suggesting two frequency generator (24.576 MHz and 22.5792 MHz) controlled by GPIO_3 (default setting) with generator output tied up to both XRHA MCLK and DAC MCLK inputs.
however:
2/ xCORE-AUDIO-HiRes-2 uses Si5351A-B04486-GT which is (according to Si labs addendum - http://www.silabs.com/internal-apps-man ... dendum.pdf) is preprogrammed to CLK1= 49.152000000 Mhz, CLK1 = 24.000000 Mhz and CLK2=45.158400000 Mhz.
So frequencies are twice higher but that's ok. But XHRA is MCLK is connected to CLK1, while DAC MCLK to CLK2 i.e. different frequencies ?! Why?
3/ GPIO_3 is tied up to RESET signal, meaning it is reprogrammed. Does it mean XHRA used in xCORE-AUDIO-HiRes-2 has a different fw revision? Or it is set by QSPI firmware?
Everything else is fairly straightforward but I am a bit stuck here. Any ideas?
Regards,
Alex
I can not get my head around clocks generation and routing on xCORE-AUDIO-HiRes-2 platform.
1/ XHRA-2HPA datasheet is sketchy on details but fairly logical - suggesting two frequency generator (24.576 MHz and 22.5792 MHz) controlled by GPIO_3 (default setting) with generator output tied up to both XRHA MCLK and DAC MCLK inputs.
however:
2/ xCORE-AUDIO-HiRes-2 uses Si5351A-B04486-GT which is (according to Si labs addendum - http://www.silabs.com/internal-apps-man ... dendum.pdf) is preprogrammed to CLK1= 49.152000000 Mhz, CLK1 = 24.000000 Mhz and CLK2=45.158400000 Mhz.
So frequencies are twice higher but that's ok. But XHRA is MCLK is connected to CLK1, while DAC MCLK to CLK2 i.e. different frequencies ?! Why?
3/ GPIO_3 is tied up to RESET signal, meaning it is reprogrammed. Does it mean XHRA used in xCORE-AUDIO-HiRes-2 has a different fw revision? Or it is set by QSPI firmware?
Everything else is fairly straightforward but I am a bit stuck here. Any ideas?
Regards,
Alex