XHRA-2HPA Reference Design Clock Issue
Posted: Wed Oct 12, 2016 3:26 pm
Hi there,
I did a quick search to see if someone had already asked about this but I didn't see anything about it.
I have designed a DAC board based around the XHRA-2HPA reference design. I have gotten to the point that I am ready to program the QSPI flash and have stumbled onto a bit of a paradox.
I am using the Si Labs Si5351A clock generator chip (preprogrammed to output 24Mhz) and in reading through the chip's documentation I have realized that in the process of reprogramming the chip over I2C it turns off all of its output clocks (not just the ones being changed).
This means that when I ask the chip to change output frequencies for the audio clock outputs it will also stop outputting the system clock which will (theoretically) freeze the XMOS chip before the rest of the I2C config. data can be sent to the clock generator chip.
This seems like it would have been a problem in the creation of the reference design but in reading the documentation I haven't seen any notes about it.
Perhaps I am missing something but before I attempt to go any further with my design I would like to clear up this point of confusion.
Thank you for your help,
-Sam
I did a quick search to see if someone had already asked about this but I didn't see anything about it.
I have designed a DAC board based around the XHRA-2HPA reference design. I have gotten to the point that I am ready to program the QSPI flash and have stumbled onto a bit of a paradox.
I am using the Si Labs Si5351A clock generator chip (preprogrammed to output 24Mhz) and in reading through the chip's documentation I have realized that in the process of reprogramming the chip over I2C it turns off all of its output clocks (not just the ones being changed).
This means that when I ask the chip to change output frequencies for the audio clock outputs it will also stop outputting the system clock which will (theoretically) freeze the XMOS chip before the rest of the I2C config. data can be sent to the clock generator chip.
This seems like it would have been a problem in the creation of the reference design but in reading the documentation I haven't seen any notes about it.
Perhaps I am missing something but before I attempt to go any further with my design I would like to clear up this point of confusion.
Thank you for your help,
-Sam