Need clarification on XSYS connector use...

[mon2]

On our dual XMOS device design, we have a 5 wire XLINK between the components. We are also applying a full XSYS header to operate with XTAG-2 interface.

Master XMOS device features a local SPI eeprom + uses XLINKs XLB0..XLB4in and XLB0..XLB4out with the 2nd XMOS device for the interconnect. Are we ok to use XLB0..XLB1in and XLB0..XLB1out subset (2 wire) with our XTAG-2 / XSYS header in addition to the above ?

Is it permitted to connect the XTAG-2 XLINK 2 wire interface to the master XMOS device (which will boot from SPI and/or JTAG during development) ? Not clear if the use of the same port pins (that belong to the 5 wire interface and is also connected to the 2nd slave XMOS device) can be used with the XTAG-2 header.

Also, confused on the use of Pin_3 on the XTAG-2 header.

Yes, the master XMOS will boot from SPI eeprom and/or JTAG during development. For this reason, we will connect MODE2 & MODE3 together and apply a pull-up to VDDIO with a jumper to ground. During development, we suspect that the XTAG-2 will drive the MODE2 & MODE3 pins HIGH (for JTAG boot) and we can hard strap with the jumper open to high for SPI boot. Is this understanding correct ?

The wording is not clear on this topic. 'Do not connect to VDDIO' ? Is there a requirement to interface the XTAG-2/XSYS pins to the 2nd device (aside from the JTAG pins) ? Specifically the MODE pins ? Believe they are not affected since the 2nd device will boot through XLINKB. The focus is with the MASTER XMOS device - correct ?

A nice document that summarizes the use of multiple XMOS devices, their interconnects with proper buffering, how to make use of the bidirectional DEBUG pin, XTAG-2 / XSYS interface would go a long way to save time.

[sethu_jangala]

Can you post the questions as distinct answerable questions?