XCore Exchange

What connection is possible to create with the G4 512-BGA chip if you would like the full 1600 Mbps in both direction along each edge in the hypergeometrical object?

I guess this one is valib, and must be very similair to the XMP-64 solution. Each node are connected to 4 other nodes.



Is it valid to use the pentachoron as well with 5 chips?
Each node are connected to 4 other nodes, whithout connections on the diagonal.


Which are the next higher possible object after 16 chips?

The first one is a hypercube.

Nice renders.

The G4 supports properly formed hypercubes only. We haven't verified anything over degree 4.

To enumerate:

• Degree 0, 1 node - a point,
  Degree 1, 2 nodes - a (short) line,
  Degree 2, 4 nodes - a square,
  Degree 3, 8 nodes - a cube,
  Degree 4, 16 nodes - a canonical hypercube a.k.a. a tessaract according to Wikipedia,
  Degree 5, 32 nodes - 2 canonical hypercubes; there's probably a name for this too.
  ...and so forth.

Clearly as you climb through the degrees, each node becomes connected to a greater number of its hyper-neighbours and so there are fewer links available to form each edge and the maximum node-to-node bandwidth is reduced. The XMP has 4 links along each edge with one dimension excepted where there are instead 3, leaving one available to be taken off the board.

A pentachoron is definitely not allowed although it does look rather attractive.

Indeed I really like the renders. Much easier to visualise than the wikipedia page for hypercubes!

trousers wrote:A pentachoron is definitely not allowed although it does look rather attractive.

Each chip can communicate with all other chips directly without the need of any extra jump, compared to the 2D sqare.
Where to place the 5:th chip on the PCB? hmmm maybe in a higher dimension :lol:

trousers wrote:Nice renders.

The G4 supports properly formed hypercubes only. We haven't verified anything over degree 4.

To enumerate:

• Degree 0, 1 node - a point,
  Degree 1, 2 nodes - a (short) line,
  Degree 2, 4 nodes - a square,
  Degree 3, 8 nodes - a cube,
  Degree 4, 16 nodes - a canonical hypercube a.k.a. a tessaract according to Wikipedia,
  Degree 5, 32 nodes - 2 canonical hypercubes; there's probably a name for this too.
  ...and so forth.

Clearly as you climb through the degrees, each node becomes connected to a greater number of its hyper-neighbours and so there are fewer links available to form each edge and the maximum node-to-node bandwidth is reduced. The XMP has 4 links along each edge with one dimension excepted where there are instead 3, leaving one available to be taken off the board.

A pentachoron is definitely not allowed although it does look rather attractive.

So what about the case with the 5D-cube (Penteract) ?
Each G4 will communicate with 5-10 other G4 chips ?



And this octeract (8D-cube) is the final evil master-thesis project in routing PCB? :twisted:

In a 2D projection we can see that one of the chip would be connected to 16 other chips (The blue dot), since it has 16 7D-cells

But don't you only have 4 links per chip?

Berni wrote:But don't you only have 4 links per chip?

The G4 can have 16 xmos links exposed in the right package.

However, the G4 has "only" an 8 bit node id so any topology with more than 256 nodes is a non-starter. That limits things to, at most, an 8 dimensional hypercube wherein each node is connected to 8 others. I think that, on some hypothetical level, one could build such a thing but rather you than me :-)

And now for something completely different: http://www.twistet.com/ticktock/n-simplexes.html
A possible insight for the mass expansion of universe, at birth.
It's beyond me, but I like it.