Sleep mode and power consumption
Posted: Mon Feb 22, 2010 2:46 am
I was hoping that the forum readers might have some insight into sleep mode and power consumption beyond what is in the XMOS documentation.
The "L series" (e.g. XS1-L1 and eventual XS1-L2) have a "PCU" (Power Control Unit?) that can interrupt the power to the core (via an external PFET) when prompted by the CPU.
The core power is resumed either in response to an external wakeup signal or a counter elapsing. (Presumably, the counter is in the PCU and clocked by SS_CLK.)
My first question would be: are the SRAM contents preserved during Sleep Mode?
Some low-power processors provide such an option, as it allows the processor to resume its state much more quickly (and thus get back to sleep mode more quickly), saving power. This would be particularly true with the XS if the entire program wouldn't fit in the OTP ROM. It does little use in being able to come out of sleep quickly if one then has to wait eons to load the software out of an SPI PROM.
Of course, powering the SRAM takes some power as well, so there is a tradeoff. The best situation is where the processor can be configured to choose whether or not to keep the SRAM powered. (That way, the software can pick the mode that best suits the anticipated Sleep Mode duration.)
I suspect that VDD powers both the CPU and SRAM, meaning that SRAM is lost during Sleep mode, but I was wishfully hoping otherwise.
On the topic of power consumption, it is a bit puzzling that:
The XS1-G2 has a budgetary power consumption of 200 uW/MHz typ. (500 uW/MHz max. for industrial, 650 uW/MHz max. for commercial).
The XS1-G4 has a budgetary power consumption of 200 uW/MHz typ. (300 uW/MHz max. for industrial, 400 uW/MHz max. for commercial).
However, the XS1-L1 has a budgetary power consumption of 450 uW/MHz typ. (It does have the footnote that it was based on pre-production targets, rather than any actual testing. Still, the part seems to be in production now.)
Based purely on the numbers from the datasheets, it seems like the G series might be a better choice for power consumption than the "low power" L series.
It begs my second question: are those numbers right? (Or, when will comparable numbers be available for the L series?)
If the G series does offer better uW/MHz and SRAM retention isn't possible in the L series, then it becomes tempting to use a G series instead of an L series and implement "PCU" equivalent external circuitry to interrupt power outright. That way, one has as good as or better sleep mode power consumption when off, and better power consumption when on.
The only loss with such an approach would be that the G series doesn't have a full equivalent to the Standby Mode in the L series. (Also, it assumes that the application would benefit from the extra processing power from a 2 or 4 core G series.)
So, my third and final question would be: is there a flaw in my logic on considering using the G series instead?
Thanks.
The "L series" (e.g. XS1-L1 and eventual XS1-L2) have a "PCU" (Power Control Unit?) that can interrupt the power to the core (via an external PFET) when prompted by the CPU.
The core power is resumed either in response to an external wakeup signal or a counter elapsing. (Presumably, the counter is in the PCU and clocked by SS_CLK.)
My first question would be: are the SRAM contents preserved during Sleep Mode?
Some low-power processors provide such an option, as it allows the processor to resume its state much more quickly (and thus get back to sleep mode more quickly), saving power. This would be particularly true with the XS if the entire program wouldn't fit in the OTP ROM. It does little use in being able to come out of sleep quickly if one then has to wait eons to load the software out of an SPI PROM.
Of course, powering the SRAM takes some power as well, so there is a tradeoff. The best situation is where the processor can be configured to choose whether or not to keep the SRAM powered. (That way, the software can pick the mode that best suits the anticipated Sleep Mode duration.)
I suspect that VDD powers both the CPU and SRAM, meaning that SRAM is lost during Sleep mode, but I was wishfully hoping otherwise.
On the topic of power consumption, it is a bit puzzling that:
The XS1-G2 has a budgetary power consumption of 200 uW/MHz typ. (500 uW/MHz max. for industrial, 650 uW/MHz max. for commercial).
The XS1-G4 has a budgetary power consumption of 200 uW/MHz typ. (300 uW/MHz max. for industrial, 400 uW/MHz max. for commercial).
However, the XS1-L1 has a budgetary power consumption of 450 uW/MHz typ. (It does have the footnote that it was based on pre-production targets, rather than any actual testing. Still, the part seems to be in production now.)
Based purely on the numbers from the datasheets, it seems like the G series might be a better choice for power consumption than the "low power" L series.
It begs my second question: are those numbers right? (Or, when will comparable numbers be available for the L series?)
If the G series does offer better uW/MHz and SRAM retention isn't possible in the L series, then it becomes tempting to use a G series instead of an L series and implement "PCU" equivalent external circuitry to interrupt power outright. That way, one has as good as or better sleep mode power consumption when off, and better power consumption when on.
The only loss with such an approach would be that the G series doesn't have a full equivalent to the Standby Mode in the L series. (Also, it assumes that the application would benefit from the extra processing power from a 2 or 4 core G series.)
So, my third and final question would be: is there a flaw in my logic on considering using the G series instead?
Thanks.