Custom Board 3xL2 not loading code

[Folknology]

Yeah the documentation on this is somewhat sparse on this point.

On the XK-1A Board the debug signal is just pulled up high with a resistor, its not buffered, just passed up the chain as is.

However on the slice kit it is pulled up and then buffered using an NC7WZ07

And the L2 datasheet says the following about it

5.9 JTAG
.....
The DEBUG_N pin is used to synchronize the debugging of multiple xCORE Tiles.
This pin can operate in both output and input mode. In output mode and when
configured to do so, DEBUG_N is driven low by the device when the processor hits
a debug break point. Prior to this point the pin will be tri-stated. In input mode
and when configured to do so, driving this pin low will put the xCORE Tile into
debug mode. Software can set the behavior of the xCORE Tile based on this pin.

This pin should have an external pull up of 4K7-47K Ω or left not connected in
single core applications.

On the block diagrams it is also shown as bidirectional.

You might just get away with a pullup, although buffering doesn't seem to be an issue looking at the slice kit design. About as clear as mud!

However if its not broken don't fix it!

regards
Al

[Redeye]

However if its not broken don't fix it!

My thoughts exactly!

However, I'd be interested to know how it's supposed to work. If it is supposed to work as both an input and an output pin as the datasheet says, then surely buffering like on the slicekit will stop it working as an input to devices the other side of the buffer?

Like I said earlier, a multi processor example/reference design might help explain a lot of these kind of questions. It does seem strange that there isn't one given how much the marketing stuff goes on about how easy it is to create multi processor designs.

[segher]

Like I said earlier, a multi processor example/reference design might help explain a lot of these kind of questions. It does seem strange that there isn't one given how much the marketing stuff goes on about how easy it is to create multi processor designs.

Have you seen the XMP-64? 16 G4s and an L1. The DEBUG pin on all
of them connected together, and with XSYS, with a 4.7k pullup to 3.3V.

The erratum means the DEBUG pin cannot drive big loads, but it works fine
as an input. And if you do not actually use DEBUG than of course this simple
construction (without any buffers) works fine as well. You could use bidirectional
buffers (like those for I2C busses) if you really care, but I wouldn't bother.