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XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Tue Jun 26, 2012 7:12 pm
by batb
Hi there,
I am experimenting with a XS1L1 LQ64 processor, the board should accept the I2S stream from the A-D chip (master), which provides also the BCK and LRCK lines.
What should I change in the code so that the XS1 will act as a slave?
Thank you!
Re: XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Tue Jun 26, 2012 8:03 pm
by Bianco
Re: XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Wed Jun 27, 2012 9:58 am
by batb
Thanks for the reply! Great,
so in slave mode I don't need the MCLK line on the Reference Design,
just BCK and WC as inputs, right?
Is it advisable to use the same port assignment as in the RD board? as the following:
BCK -> xs1_port_1A (X0D0),
LRCK -> xs1_port_1C (X0D10),
SDI -> xs1_port_1I (X0D24)
keeping BCK and LRCK shared with SO and SCL from flash memory?
Suggestions welcome.
Thank you.
Re: XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Sat Aug 25, 2012 9:32 am
by batb
What I meant was using the RD with the XS1 as a slave,
where the LRCLK and BCLK are not internally generated, as in the standard RD board,
but are input from the Codec (in my case A-D converter chip),
format is I2S, so I think it should be natively supported by the RD code (am I wrong?)
What I read from page 15 of the Software Design Guide document:
Configuration with the CODEC set as I2S master, and the XCore as a slave,
this configuration is achieved by commenting out the following line in
customdefines.h :
what puzzles my mind is how do I get the LRCLK and BCLK ports
behave as inputs...
but
main.xc starts with:
Code: Select all
/* Audio I/O */
on stdcore[0] : buffered out port:32 p_i2s_dac[1] = {XS1_PORT_1D};
on stdcore[0] : buffered in port:32 p_i2s_adc[1] = {XS1_PORT_1I};
on stdcore[0] : buffered out port:32 p_lrclk = XS1_PORT_1C;
on stdcore[0] : buffered out port:32 p_bclk = XS1_PORT_1A;
on stdcore[0] : port p_mclk = XS1_PORT_1M;
on stdcore[0] : buffered out port:32 p_spdif_tx = XS1_PORT_1L;
on stdcore[0] :in port p_for_mclk_count = XS1_PORT_1E;
should I change port_1c and port_1a to
buffered in port ?!
Has anyone used this configuration?
Any help greatly appreciated.
Thank you!
Re: XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Thu Sep 06, 2012 7:48 am
by batb
No, it doesn't work by simply decommenting the line.
Anyone used the Reference Design with the XCore as slave?
Any suggestion greatly appreciated !!
T.I.A.
Re: XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Sat Sep 15, 2012 6:36 pm
by batb
This is just driving me nuts!
Is it possible?
It seems that the USB Audio 2.0 2-channel Reference Design board cannot be operated with codec as master and XCore as slave?!
Just tried to decomment the line in the 'customdefines.h', as I wrote in my previous msg, put the codec in slave mode by pulling pin 13 high....
result: MCLK clock waveform is present, but the Codec cannot generate any clock (SCLK and LRCLK), even the SDI line seems dead,
the CEntrance driver doesn't recognize the board.
In the default configuration (default binary .xe file, XCore as master, generating all the clocks, and the Codec as a slave, with pin 13 pulled low), everything works fine.
The CEntrance driver correctly recognizes the RD board, and is able to change the sample rate settings if you want.
Even tried to make some recordings through a recording software on my PC (WaveLab),
all went ok.
I would like to find a way to experiment with my RD board with the XCore as a slave.
Please any help, suggestion and the like more than welcome!!
Re: XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Fri Aug 23, 2013 12:02 am
by Ross
The data sheet for the CS4270 states:
Pin 7:
Serial Audio Data Output (Output) - Output for two’s complement serial audio data. This pin must be pulled up or down through a 47-k resistor to select Master or Slave Mode.
Re: XS1L1 LQ64 and RD modified to slave (I2S)
Posted: Mon Jan 13, 2014 1:12 pm
by mhelin
In current USB Audio 2.0 Reference Design MCLK is still needed in slave configuration, but I think that requirement could be removed and SCLK used as a reference clock (if needed at all, at least Apple proposes that if the driver can use implicit feedback provided by input samples the explicit feedback endoint is not required at all), but then the (USB) explicit feedback interval should be increased a little bit (I think at least doubled to 256 SOF microframes but I haven't done proper calculations) to get the proper precision (was it 10:10 bit fractional or 10:14?).