Matching Clocks to Data with high speed transfer
Posted: Fri Mar 23, 2012 4:32 am
I am doing an exercise on joining XMOS to a FPGA, and need highest speed transfers, with fewest wires.
Some of this info is 12b from ADC, and a QuadSPI link appealed.
This will likely have two links, one running at close to 100%, and another link that will ideally self-pace by just not sending CLK edges, when data is not valid. ( ie rather like SPI )
It seems however, that XMOS lacks this implicit Clock edge gating, and says cryptic things like
The data driven on one edge continues to be driven on subsequent edges.
and I see SPI libraries that actually use transmitted data as a clock (?!), and other threads about extra clocks at high speed, when using stop_clock()
I can find mention of partout(), but no examples of the speed of that, and even the description does not actually state that the clocks produced match the data ?
Q: Can I use partout(), to send 24 bits over a 4w port, and produce the needed 6 clock edges whilst doing so ?
If yes, what is the speed limit of this, and if I call it multiple times, does the clock merge to have no gaps, or is there a ?? cycle delay overhead in this ?
I do not really want to send 32 bits with 8 discarded, as that wastes bandwidth, and adds complexity.
Some of this info is 12b from ADC, and a QuadSPI link appealed.
This will likely have two links, one running at close to 100%, and another link that will ideally self-pace by just not sending CLK edges, when data is not valid. ( ie rather like SPI )
It seems however, that XMOS lacks this implicit Clock edge gating, and says cryptic things like
The data driven on one edge continues to be driven on subsequent edges.
and I see SPI libraries that actually use transmitted data as a clock (?!), and other threads about extra clocks at high speed, when using stop_clock()
I can find mention of partout(), but no examples of the speed of that, and even the description does not actually state that the clocks produced match the data ?
Q: Can I use partout(), to send 24 bits over a 4w port, and produce the needed 6 clock edges whilst doing so ?
If yes, what is the speed limit of this, and if I call it multiple times, does the clock merge to have no gaps, or is there a ?? cycle delay overhead in this ?
I do not really want to send 32 bits with 8 discarded, as that wastes bandwidth, and adds complexity.