Clocked ports, sampling on rising clock

[ale500]

Reading the pdf on ports, I see that all transition for clocked ports happen on the falling edge of the clock (and using), is there a way to sample on the rising edge of the clock. Should the "invert state of pin" set_port_inv function be called on the port that output the clock to get this effect ? or how is it achieved ?

[MaxFlashrom]

Reading the pdf on ports, I see that all transition for clocked ports happen on the falling edge of the clock (and using), is there a way to sample on the rising edge of the clock. Should the "invert state of pin" set_port_inv function be called on the port that output the clock to get this effect ? or how is it achieved ?

By default ports sample on the rising edge of the clock and output on the falling edge of the clock.
If the clock is generated internally, from the(possibly divided) reference clock you can use

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/**
 * Sets a port to sample delay mode. This causes the port to sample input data
 * on the falling edge of its clock.
 * \param p The port to configure.
 * \sa set_port_no_sample_delay
 */
void set_port_sample_delay(void port p);

This might be the case if you want to clock a port half a clock cycle after another port. It's unclear to me whether this has any effect on clocking data out.

If the port's clock is derived from a sampled external master clock(It's sampled into the XS1 clock domain by the 400MHz clock. Note this introduces some jitter) Then one can invert that clock input before it drives an internal clock block. This gives the effect that relative to this sampled clock, a port looks like it's clocked out on the rising edge relative to this external clock.

One can use

Code: Select all

/** Configures a 1-bit port to invert data which is sampled and driven
 *  on its pin. If the port is not a 1-bit port, an
 *  exception is raised. If the port is used as the source for a
 *  clock then setting this mode has the effect of the swapping the
 *  rising and falling edges of the clock.
 *  \param p The 1-bit port to configure.
 *  \sa set_port_no_inv
 */
void set_port_inv(void port p);

#include <xs1.h>
for these functions.

Hope this helps
Max.

[ale500]

I see... then set_port_inv is used for input and not for outputs... very Interesting!

[MaxFlashrom]

I see... then set_port_inv is used for input and not for outputs... very Interesting!

It inverts both inputs and outputs, as far as I understand:
The manual says

A 1-bit port can be set to invert all data on both input and output

I don't know if it works for wider ports. It'll probably throw an exception if it doesn't; I've not tried it.
Max

[ale500]

I will have to test it... now to find something that requires it... ;-)

[ale500]

A have another question, the manual says that inputs can sample at 60MHz from an external clock... does it means that we can sample at higher frequencies from the 100 MHz reference clock ?

[rp181]

I'm pretty sure that the pins can operate at max 100 MHz (10 ns response time), I remember reading that somewhere....
The clock blocks only go up to 50 MHz (I think), so maybe this is bit banged?

I know... I just exude confidence... ;)

[ale500]

The clock blocks go to 50, yes. Selecting 1 as division will mean 100/2... but the reference clock can be used without a prescaler I think...

[rp181]

Ports are, by default, clocked by the reference clock. As for getting the clock:

Code: Select all

clock ref = XS1_CLKBLK_REF;

Just found this:
https://www.xmos.com/download/public/XS ... .02%29.pdf

[ale500]

Yes, exactly that is what I meant. If one uses a buffered port of width 8, (4 bytes FIFO) then there is enough time to put the data in memory and wait for the next round. I wonder if that could be used to access 100 MHz SDRAM...