Clock Blocks

[rp181]

Are clock blocks hardware resources? What causes them to go slower? I set up a clock block, for read an SPI line. I need to be able to read the ADC at at least 800 kHz, which means a clock of ~20 MHz, or a div of 4. However, with a div of anything less than about 10, the clock output is very bad, and messes everything up:


The code:

Code: Select all

...
out port spi_ss = XS1_PORT_1E;
out port mosi = XS1_PORT_1D;
out buffered port:8 sclk = XS1_PORT_1C;
in buffered port:8 miso = XS1_PORT_1F;
clock blk1 = XS1_CLKBLK_1;
clock blk2 = XS1_CLKBLK_2;
...

int main(void){
	unsigned short data;
	sendShort((unsigned short) 0b1111111111110000); //configuring the ADC. MOSI is bit banged.

	configure_clock_rate(blk1, 100, 4);
	configure_out_port(sclk, blk1, 0);
	configure_clock_src(blk2, sclk);
	configure_in_port(miso, blk2);
	clearbuf(sclk)
	;                                        //anyone else's autoformat do this?
	start_clock(blk1)
	;
	start_clock(blk2)
;	sclk <: 0xFF;

while (1) {
		spi_select();
		data = spi_in_short(); // SPI class
		spi_deselect();
		delay(); //10ns delay, so the ADC doesn't miss the pulse
	}
}

EDIT: heh... a Logic analyzer problem...

[rubenc]

Are clock blocks hardware resources? What causes them to go slower? I set up a clock block, for read an SPI line. I need to be able to read the ADC at at least 800 kHz, which means a clock of ~20 MHz, or a div of 4. However, with a div of anything less than about 10, the clock output is very bad, and messes everything up:


The code:

Code: Select all

...
out port spi_ss = XS1_PORT_1E;
out port mosi = XS1_PORT_1D;
out buffered port:8 sclk = XS1_PORT_1C;
in buffered port:8 miso = XS1_PORT_1F;
clock blk1 = XS1_CLKBLK_1;
clock blk2 = XS1_CLKBLK_2;
...

int main(void){
	unsigned short data;
	sendShort((unsigned short) 0b1111111111110000); //configuring the ADC. MOSI is bit banged.

	configure_clock_rate(blk1, 100, 4);
	configure_out_port(sclk, blk1, 0);
	configure_clock_src(blk2, sclk);
	configure_in_port(miso, blk2);
	clearbuf(sclk)
	;                                        //anyone else's autoformat do this?
	start_clock(blk1)
	;
	start_clock(blk2)
;	sclk <: 0xFF;

while (1) {
		spi_select();
		data = spi_in_short(); // SPI class
		spi_deselect();
		delay(); //10ns delay, so the ADC doesn't miss the pulse
	}
}

EDIT: heh... a Logic analyzer problem...

I saw your picture, I would like to ask you wich logical analyzer are you using?
I dont know it but seems nice.
Thankyou!

[MaxFlashrom]

Looking at the logic analyser screen shot, and its title bar, it appears he's using an analyser from
http://www.saleae.com/logic/

Disclaimer: I have no affiliation with these guys, and have never used one of their products, which may or may not be excellent!

Max.

[rp181]

Yes, that's the one. Works well!

EDIT: Just to be clear, when I said it was a problem with the logic analyzer, it was really me. It supports sampling up to 24 MHz, but since my computer's USB is too slow, it defaulted to 16 MHz, missing some edges giving me the strange results. It is a very good USB analyzer!

[kster59]

You do realize that if you are measuring a 20mhz signal you need AT LEAST a 40mhz sampling freq. To accurately capture it you will need a 100mhz sampling freq.

Run it in the simulator if you don't have a fast enough logic analyzer.

[rp181]

I know you're supposed to go faster, but honestly, I didn't see any problems @ 24MHz on a 20 MHz singal. The times were a little bit off, but was accurate enough (is it working or not?).

[kster59]

Whatever you see is pure luck or complete garbage if sampling rate < 1/2 freq. Google Nyquist theorem.

[segher]

But the maximum frequency in a signal that does x bits per second is x/2 Hz,
so you're fine if you sample slightly above x samples per second (you need
slightly above, because clock jitter and inaccuracies will get you slightly
below otherwise).

[MaxFlashrom]

Whatever you see is pure luck or complete garbage if sampling rate < 1/2 freq. Google Nyquist theorem.

You meant, of course, "Whatever you see is pure luck or complete garbage if sampling rate < (2 * freq.)"
One must sample twice the frequency of the highest frequency component (exceptions for band-limited signals apart) to avoid aliasing.

But the maximum frequency in a signal that does x bits per second is x/2 Hz,
so you're fine if you sample slightly above x samples per second (you need
slightly above, because clock jitter and inaccuracies will get you slightly
below otherwise).

In practical terms for "square-wave frequencies" where one is not too bothered about the shape of the rise fall time, this works.
Fourier series shows that frequencies in a square wave with a fundamental of x Hz extend much higher than x, and for an "ideal" square wave, with brick-wall edges, to infinity. Interestingly enough one cannot, even then, achieve a square wave with a flat top and bottom.
See

http://en.wikipedia.org/wiki/Gibbs_phenomenon

In the real world square waves have sloping edges and are band-limited

Max.