JTAG Load Program and Run
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- New User
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JTAG Load Program and Run
I am developing software which utilizes the JTAG interface to the XS1-G4. I am having issues finding the Instruction Register values which would allow me to load a program to memory. In addition once a program is loaded what is the best way to set the program counter to execute code at a given location. I did notice the DBG_SCRATCH[0] register could be used to set the program counter on a debug interrupt.
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- XCore Expert
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You can have a look at my tools, http://git.infradead.org/users/segher/dis-xs1.git.
First, you set the JTAG mux to point to the core you want (or the sswitch if that's what you're
after): write the 4-bit instruction 0100 to the mux IR reg, and the 4-bit number 8+core#
(or 1 for the sswitch) to the DR.
Now you have some extra regs in your JTAG chain: a 10-bit instruction reg for the pswitch
or sswitch you enabled.
To read from a switch reg, you write the 10-bit number xxxxxxxx01 to the IR, and read
the 32-bit value from DR; to write to a switch reg, the IR is xxxxxxxx10.
To read the memory, you first need to switch the core into debug mode: write 1 to pswitch
reg 5.
To read a single word from memory, write the address to pswitch reg x'22, write command
number 2 to pswitch reg x'21, and read the result from pswitch reg x'24 (after enough delay;
the JTAG stuff is slow enough that you will not usually need any).
To write a word to memory, it's address to x'22, value to x'24, command 3 to x'21.
To set the PC, write the value to PS reg x'110b: reg # to x'22, value to x'24, command 5 to
x'21.
Then you need to take the core out of debug mode: 0 to pswitch reg 5, command 9 to x'21.
And that's it! See the code for more commands, there are 12 or so. "run.c" uploads 64kB
of program and starts it at x'10000, "jtag.c" contains all the lower-level primitives, there are
some more programs to do other things.
dump-rom will let you figure out the debugger for yourself, btw ;-)
First, you set the JTAG mux to point to the core you want (or the sswitch if that's what you're
after): write the 4-bit instruction 0100 to the mux IR reg, and the 4-bit number 8+core#
(or 1 for the sswitch) to the DR.
Now you have some extra regs in your JTAG chain: a 10-bit instruction reg for the pswitch
or sswitch you enabled.
To read from a switch reg, you write the 10-bit number xxxxxxxx01 to the IR, and read
the 32-bit value from DR; to write to a switch reg, the IR is xxxxxxxx10.
To read the memory, you first need to switch the core into debug mode: write 1 to pswitch
reg 5.
To read a single word from memory, write the address to pswitch reg x'22, write command
number 2 to pswitch reg x'21, and read the result from pswitch reg x'24 (after enough delay;
the JTAG stuff is slow enough that you will not usually need any).
To write a word to memory, it's address to x'22, value to x'24, command 3 to x'21.
To set the PC, write the value to PS reg x'110b: reg # to x'22, value to x'24, command 5 to
x'21.
Then you need to take the core out of debug mode: 0 to pswitch reg 5, command 9 to x'21.
And that's it! See the code for more commands, there are 12 or so. "run.c" uploads 64kB
of program and starts it at x'10000, "jtag.c" contains all the lower-level primitives, there are
some more programs to do other things.
dump-rom will let you figure out the debugger for yourself, btw ;-)
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- New User
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segher,
Thank you for the link to your project and the description of the additional IR commands. Are you aware of any document from xmos detailing this additional functionality? In addition, is the functionality present in the bootloader rom or inherently through the architecture? I have been through the datasheets describing the XS1 architecture and chips independently and was unable to determine this functionality.
Thanks again for your time.
Thank you for the link to your project and the description of the additional IR commands. Are you aware of any document from xmos detailing this additional functionality? In addition, is the functionality present in the bootloader rom or inherently through the architecture? I have been through the datasheets describing the XS1 architecture and chips independently and was unable to determine this functionality.
Thanks again for your time.
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- XCore Expert
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- Joined: Sun Jul 11, 2010 1:31 am
The IR commands and the mux controller are described in some of the datasheets.fluxint wrote:Thank you for the link to your project and the description of the additional IR commands. Are you aware of any document from xmos detailing this additional functionality?
The PS regs and pswitch regs are let's say sparsely documented.
The commands you give the debugger through the scratch regs (20, 21, etc.) are purelyIn addition, is the functionality present in the bootloader rom or inherently through the architecture?
software in the ROM. I'm not sure if this is documented anywhere. Most of how the debugger
works internally is documented (the SPC reg etc.)
If you need any more help, please ask (here, so that people can look it up later).