i'm working on a board of my own and have run into a problem: the pin names for the Xsys connector do not appear to have a naming correlation with the chip pinout. some of the pin names are similar but it seems pretty wonky over all.
i've read the XS1-LO1A-LQ64 datasheet and the XTAG-2 Hardware manual, the jtag schematic and it's driving my crazy.
there doesnt seem to be any information specifically for the interface that identifies which pins connect to the XMOS chip pins.
help.
Xsys naming scheme mismatch
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Hi,
which part is unclear?
All names in the XTAG-2 hardware manual are written from the XTAG2 as viewpoint.
i.e.:
Pin 5 on XSYS connector, named TDSRC (Test Data Source) should be connected to TDI (Test Data In) of your XMOS chip.
Pin 13 on XSYS connector, named TDSNK (Test Data Sink) should be connected to TDO (Test Data Out) of your XMOS chip.
I recommend to take a look at the XK-1A schematics, since they incorporate two XSYS headers.
which part is unclear?
All names in the XTAG-2 hardware manual are written from the XTAG2 as viewpoint.
i.e.:
Pin 5 on XSYS connector, named TDSRC (Test Data Source) should be connected to TDI (Test Data In) of your XMOS chip.
Pin 13 on XSYS connector, named TDSNK (Test Data Sink) should be connected to TDO (Test Data Out) of your XMOS chip.
I recommend to take a look at the XK-1A schematics, since they incorporate two XSYS headers.
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let's simplify this.
how do you connect the chip to the Xsys connector?
how do you connect the chip to the Xsys connector?
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I currently dont have time to draw it for you.
I'll answer your question on friday or saturday if no one has come with a satisfying answer.
I'm sorry for that.
Also are you using a spi flash and have you thought about generating a proper reset signal after powering up (using a power-on-reset controller)
I'll answer your question on friday or saturday if no one has come with a satisfying answer.
I'm sorry for that.
Also are you using a spi flash and have you thought about generating a proper reset signal after powering up (using a power-on-reset controller)
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draw? just make a list of connections. i.e. TDI->XSYS_16Bianco wrote:I currently dont have time to draw it for you.
yesare you using a spi flash
yes, i was just trying to keep the image simple and straightforwardand have you thought about generating a proper reset signal after powering up (using a power-on-reset controller)
i have time. :)I'll answer your question on friday or saturday if no one has come with a satisfying answer.
I'm sorry for that..
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so... does anyone know?
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Hi gravis, i am sorry that i did not get back to you earlier and did not respond to your pm of last week.
For a minimalist system this would do:
Make sure that there is a proper reset signal generated on the board when no XTAG is connected.
Also this is more a logic diagram than an electrical one: you might want to add buffers here and there.
The TRST_N of the XTAG2 is not used as such any more in the new tools, you CAN connect it to TRST_N of the XMOS to generate the test reset signal on startup (you still need to generate a proper test reset signal when no XTAG is connected), but it can also be used to toggle the boot select mode pins, which is the new use: if no XTAG is connected it will boot from SPI and if you load code to the board through the XTAG it will boot in 'wait for JTAG' mode. The JTAG state machine reset is not dependent of the TRST_N pin on the XMOS side other than that it must be pulled high at startup, ORing it with the RST_N will satisfy this. (The current tools use a rendezvous between TCK and TMS to reset the JTAG state)
I highly recomment to look at the schematics of several L1 systems to inspire you:
XK-1A (might be a bit confusing with two XTAG connectors for chaining), Minimal L1 system (can't find it back on the site), Corin's L1 DIP module.
For a minimalist system this would do:
Code: Select all
XSYS
pin# NAME <--> XMOS
1 5V
2 NC
3 TRST_N MODE2, MODE3
4 GND (Target board GND)
5 TDSRC TDI
6 XL1_UP1
7 TMS TMS
8 GND (Target board GND)
9 TCK TCK
10 XL1_UP0
11 DEBUG
12 GND (Target board GND)
13 TDSNK TDO
14 XL1_DN0
15 RST_N RST_N, TRST_N
16 GND (Target board GND)
17 UART_RX
18 XL1_DN0
19 UART_TX
20 GND (Target board GND)
Also this is more a logic diagram than an electrical one: you might want to add buffers here and there.
The TRST_N of the XTAG2 is not used as such any more in the new tools, you CAN connect it to TRST_N of the XMOS to generate the test reset signal on startup (you still need to generate a proper test reset signal when no XTAG is connected), but it can also be used to toggle the boot select mode pins, which is the new use: if no XTAG is connected it will boot from SPI and if you load code to the board through the XTAG it will boot in 'wait for JTAG' mode. The JTAG state machine reset is not dependent of the TRST_N pin on the XMOS side other than that it must be pulled high at startup, ORing it with the RST_N will satisfy this. (The current tools use a rendezvous between TCK and TMS to reset the JTAG state)
I highly recomment to look at the schematics of several L1 systems to inspire you:
XK-1A (might be a bit confusing with two XTAG connectors for chaining), Minimal L1 system (can't find it back on the site), Corin's L1 DIP module.
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hello,
there seems to be a little failure on pin 14 and 18. Both with the same name?
Like in the XK-1A schematic, pin 18 should be XL1_DN1.
BTW: Is it possible to use the JTAG-Ports TDO/TDI for the own schematic after booting all up?
Without the TCK there should nothing disturb...
I only want to switch an optocoupler/mosfet on and off, so there must no full-function-port.
(want not to waste a "real" port) Maybe with some asm-code?
CU
Volker
there seems to be a little failure on pin 14 and 18. Both with the same name?
Like in the XK-1A schematic, pin 18 should be XL1_DN1.
BTW: Is it possible to use the JTAG-Ports TDO/TDI for the own schematic after booting all up?
Without the TCK there should nothing disturb...
I only want to switch an optocoupler/mosfet on and off, so there must no full-function-port.
(want not to waste a "real" port) Maybe with some asm-code?
CU
Volker