Making connection betwin FPGA and XS1-G4

[nassim]

Hi all :D

have any one try to connect XMOS processor with an FPGA or create an interface exchange data between them.

what i want to try is to create an interface with an BUS data/addresses witch is also connected with other processor.

exp : - Make interface between XS1-G4 and wishbone bus witch is connect with OpenRisc1200 processor
or
- Make interface between XS1-G4 and PLB bus witch is connect with Microblaze/powerPC processor

So, what XMOS can do in this project => create all peripheral interface in XS1-G4 (DSP,UART/USB, MAC/ETH, GPIO ...)
*DSP => 2 Core
*UART/USB and GPIO => 1 Core
*MAC/ETH => 1 Core

the final idea is to port linux in openrisc1200 (including MMU and also interface with DDRS-DRAM/DDR2) and test all peripheral (UART ....) in xmos

and creat PCB board include one FPGA with is smal (spartan-3E500) because include just 2 IP openrisc1200 and DDR; connected with XMOS witch include all peripheral.

all comment are welcome. thanks

[ale500]

There is a XLink implementation in Verilog for FPGAs. I think it supports the G4 and maybe with some tweaks can also support the L devices. I'm planning on using it myself. I think it would be best for your case too because you do not have to bit-bang a Data/Address bus on the XMOS but you will have to implement it as a memory-mapped device for the openRISC.
Now that I think of it, if you have your own custom board with a G4 and a FPGA then an Address bus/Data bus model would work. If you have a XC-1 or 1A then the story is a bit different, the 1A has not enough pins for a very wide address bus (the XC-1 does but it has been discontinued). Which board are you going to use ?

Have fun :)

[nassim]

hi ale and thanks for your reply.

i use this board Xlinx SPARTAN-3E500K (FPGA) and XC-2 Ethernet Kit (XMOS).

Spartan-3E500k is connected automatically to DDR SDRAM 64MB.
XMOS XC-2 have an ethernet interface.

your board is amazing :shock: , so if you what then next step is to connect FPGA to SDRAM and all peripheral is connected to XMOS and not FPGA (UART, ETH.....).

so i thin for my case is to create XLINK to wishbone

[ale500]

Thanks :)

A Xlink peripheral with wishbone interface opens the door to many other soft processors...

[nassim]

yes i am with you in this ;) . i start with spartan-3E500 and XK1 (i still wait XC-2) and try to replace the UART IP core of opencore with an UART in XMOS chip then make connection between them (XLINK to Wishbone).

if it's all ok, that will be easy with other IP and move to porting LINUX :D . ALL this is the first step to my VOIP project.