Connecting Two xCORE-200 explorerKIT Using xTAG and xCONNECT

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Connecting Two xCORE-200 explorerKIT Using xTAG and xCONNECT

Postby johned » Thu Sep 08, 2016 11:03 am

This example will consider connecting two xCORE-200 eXplorer boards to create a 32 tile network.

The first thing to consider is the xTAG connectivity.

The easiest thing to do is to daisy chain the xSYS connectors, using some header connectors and ribbon cable.
Note : it is important to keep the cables as short as practical.
For clarity, xSYS refers to the connectors and xTAG to the adapter.

Here is the connectivity :
xTAG TDI to TDI of board one
TDO of board one to TDI of board two
TDO of board two to xTAG TDO
xTAG TCK to TCK on both boards
xTAG TMS to TMS on both boards
The four XSYS link wires (XLUP0/1 and XLDN0/1) between the xTAG and boards one

Now you should have full xTAG and xSCOPE access
You can skip RST_N, DEBUG_N, and MSEL; they are not used for xCORE200 at present but if you want to be on the safe side gang them all up to the appropriate xTAG signals.

Pinout for the xsys connector is in the schematics : ... 1.2%29.pdf

When you scan the JTAG scan chain, using xrun, you should get :

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> xrun -l

Available XMOS Devices

  ID    Name                    Adapter ID      Devices
  --    ----                    ----------      -------
  0     XMOS XTAG-3             YgYZJhvL        O[0..1]
It is possible that the JTAG signals are not enjoying the extra cable length added into the scan chain so it might be necessary to slow down the JTAG as follows :

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> xrun --jtag-speed 1 xxx.xe
This will run the JTAG at half speed, in case this is the problem.

In order to build an application to run on the new 32 core network it is necessary to modify the .xn file. The attached file will provide the basic functionality.
This includes a single xCONNECT link between the boards, to start with :

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<LinkEndpoint NodeId="0" Link="4"/>
<LinkEndpoint NodeId="3" Link="4"/>
The next connections to make between the boards are the xCONNECT links.
These can be used by xSCOPE, channels or interfaces.
Referring to Chapter 16 "xCORE-200 explorerKIT Portmap" in the xCORE-200 explorerKIT Hardware Manual we see that there are several options.
xCONNECT channels can operate in 2 wire or 5 wire mode. The tradeoff is that 2w mode frees up more pins for GPIO and 5w mode provides higher inter-processor bandwidth.
For this example, we will just connect Link 4 between the boards as per the .xn file entry :

Please make the following connections :

Board one : E0 in (J3 pin 32) to Board two : E0 out (J3 pin 34)
Board one : E0 out (J3 pin 34) to Board two : E0 in (J3 pin 32)
Board one : E1 out (J1 pin 24) to Board two : E1 in (J1 pin 25)
Board one : E1 in (J1 pin 25) to Board two : E1 out (J1 pin 24)

Notes :
- Link 4 (also known as Link E in the xCORE-200 explorerKIT Hardware Manual) has been chosen for this example because the pins do not clash with any other functionality on the xCORE-200 explorerKITs (e.g. LEDs or buttons).
- These ports are unavailable if RGMII or USB enabled on tile 1
- Link 4 can also be used in 5 wire mode on the xCORE-200 explorerKIT, at the cost of GPIO pins
You might find the xCORE-200 Devices Portmap useful for allocating GPIO

- xCONNECT Architecture - ... 1.0%29.pdf
- XS1 Link Performance and Design Guidelines - ... s(2.0).pdf
- xCORE-200 explorerKIT documentation and design information (including the Portmap) :

In order to booth both boards from their local FLASH you can follow this good example that uses two startkits :
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Postby infiniteimprobability » Fri Sep 09, 2016 11:34 am

Hi John,
interesting and useful post. Do you have any comment on required signal integrity? I am aware that the links are fast there is no error checking in the link protocol. What would make sense here?
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Postby johned » Fri Sep 09, 2016 11:50 am

Morning, II,

Some comments from a very knowledgeable chap ;-)

Check that the xCONNECT signals will be guaranteed low at start (either very short traces or a 10k pull down). Series termination at source is preferable too (33ohm).

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Postby lorenzochiesi » Tue May 07, 2019 1:02 pm

Hi All,

Exist any way to connect 2 x xC200 MC-Audio 2V0 Developement kit?

Is is possible to link the CPU using only XLUP0/1 and XLDN0/1 from xSYS connector?
Maybe renouncing to xSCOPE functionalities and using only JTAG for programming/Debugging?

I'm struggling on xCONNEDCT and xLINK documentation but seems one of the most obscure features of xCORE

Many thanks for any hints,
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Postby TonyXiao » Fri May 31, 2019 9:46 am

Hi John,

from your post xn file, it seems both of the two xmos are connected with spi flash.
is it possible to connect only one spi flash? does it works?

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Postby johned » Mon Jun 03, 2019 3:56 pm

Hi Tony, yes, the MC boards each have their own flash but if you connect the boards via xCONNECT links then you can modify the .xn file so both devices boot from the same.
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Postby TonyXiao » Wed Jun 05, 2019 4:49 am

Hi John,
Thanks a lot for your reply.
now i followed your procedure to one explorer board(slave)and one MC board(master), use xrun -l, 2 xmos can be found, but i can not run and flash program.
when run, it notify:xrun: First stage multi-node boot failed, please check XN file and Xmos link connectivity.
when flash, it notify: xflash: Error: F03105 Node "2" is configured to boot from XMOSLINK but no device is configured to boot it.

i have double checked the connection,it seems all right. the only difference to your procedure, i remove the SPI FLASH and set the slave xmos boot procedure by set the X0D04\X0D05\X0D06 to 0\0\1 as order. isn't it a must set?

i post my xn file and Connection Diagram here, any clue or suggestion will be appreciated.

BR, Tony
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