XS-L1A TQFP 128 Pins and Links

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
snoopy
Member++
Posts: 28
Joined: Wed Dec 01, 2010 5:46 pm

XS-L1A TQFP 128 Pins and Links

Postby snoopy » Thu Jan 20, 2011 1:04 am

I don't know if I've missed something fundamental or am being daft about this but I can't seem to get something about the IO pins.

This chip has 42 IO pins. Now I need 2 of them to be Links and the rest for IO. But when you look at the pin table the links a smack bang in the middle of the 32 port line.

Is it possible to shift around the XN file so that i can still use the remaining 40 ports? Or maybe shift bits individually into those ports.

I need the ports to constantly be pumping out signals so I can't afford to temporarily disable them and use them for links, then back as ports again.

Any suggestions :?:

Thanks in advanced
Jake
ale500
Respected Member
Posts: 259
Joined: Thu Sep 16, 2010 9:15 am

Postby ale500 » Thu Jan 20, 2011 7:45 am

You need at least 4 pins for a 2-bit XLINK (or 10 for the 5 bit version). It is not possible to reconfigure it and have the links on some other pins, sadly. If you do not need all pins to be high speed you may go away with an IO Expander, for slow things like LEDS, buttons and the sort. A slave uC like a PIC or an AVR can be also helpful performing simple tasks like data acquisition and so on.
bearcat
Respected Member
Posts: 277
Joined: Fri Mar 19, 2010 4:49 am

Postby bearcat » Thu Jan 20, 2011 9:28 am

If you need XLINKA, then no you can't use the full 32 bit port. If you can use XLINKB, then you can.

If you look at the XS1-L1 128 manual table 2.2 - Port Pin table. You can see how the pins break down. You do not need to use a 32 bit port to access all the pins. You can use 4, 8, or 16 bit ports to access a subset of the pins and break up the output into a couple of statements to get all the pins you need.

If you are going to be driving different pins within multiple threads, then you do want to break it down into smaller ports. XC doesn't allow multiple threads to access the same pins without some tricks.
snoopy
Member++
Posts: 28
Joined: Wed Dec 01, 2010 5:46 pm

Postby snoopy » Thu Jan 20, 2011 2:44 pm

Ok so how about this then....

I set the links to X0LB so I can still use the 32 port line.

Can I also use the Port 16B? Cause I can't see why that won't work seeing as they don't conflict.

Thanks,
Jake
ale500
Respected Member
Posts: 259
Joined: Thu Sep 16, 2010 9:15 am

Postby ale500 » Thu Jan 20, 2011 2:57 pm

Yes, P16B and P1A, B, C, D, E, F, G, H, I, J, K, and L.
snoopy
Member++
Posts: 28
Joined: Wed Dec 01, 2010 5:46 pm

Postby snoopy » Thu Jan 20, 2011 3:00 pm

Thats great. Thanks for the support :D

Out of curiosity then....If we can use all these ports why is the IO listed as 42 pins where if you use the 32 and 16 there is already 48 there?

Jake
bearcat
Respected Member
Posts: 277
Joined: Fri Mar 19, 2010 4:49 am

Postby bearcat » Thu Jan 20, 2011 8:10 pm

Not sure where you saw 42 pins. The L1 manual says 64 user pins, including all I/O. 12 of those can only be used as 1 bit ports.

One additional note, If you plan on using the USB3318 USB transceiver, then you lose some I/O. Reference the design checklist in that case.
ale500
Respected Member
Posts: 259
Joined: Thu Sep 16, 2010 9:15 am

Postby ale500 » Thu Jan 20, 2011 9:26 pm

The '128 has 64 IOs the '64 has only 42.
snoopy
Member++
Posts: 28
Joined: Wed Dec 01, 2010 5:46 pm

Postby snoopy » Thu Jan 20, 2011 9:50 pm

Ye I saw the 64 IO lines in the reference guide. This is what was confusing me :

http://www.xmos.com/products/silicon+devices

There it says 42 IO but everywhere else its 64. Not sure how to tell them about the error. I'll send an email to someone.

Jake
snoopy
Member++
Posts: 28
Joined: Wed Dec 01, 2010 5:46 pm

Postby snoopy » Thu Jan 20, 2011 9:53 pm

Coool....all sorted :D

Thanks to everyone for your support

Jake

Who is online

Users browsing this forum: No registered users and 1 guest